Tinsel: a manythread overlay for FPGA clusters
Accepted version
Peer-reviewed
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Abstract
Commodity FPGA boards with advanced networking facilities have great potential in the construction of high-performance compute clusters that scale. However, low-level design tools and long synthesis times are major barriers to productivity for application developers. In this paper, we explore the potential of a distributed soft-processor overlay, programmed in software at a high-level of abstraction, to deliver a useful level of performance for FPGA clusters. In particular, we demonstrate the use of hardware multhreading to achieve a fast, space-efficient, high-throughput overlay, and compare a 12-FPGA instance of it (12,288 RISC-V threads) against a conventional Xeon cluster on the problem of distributed graph processing.
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Keywords
4606 Distributed Computing and Systems Software, 46 Information and Computing Sciences, 3301 Architecture, 33 Built Environment and Design
Journal Title
2019 29th International Conference on Field Programmable Logic and Applications (FPL)
Conference Name
2019 International Conference on Field Programmable Logic and Applications
Journal ISSN
1946-1488
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Publisher
IEEE
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Sponsorship
Engineering and Physical Sciences Research Council (EP/N031768/1)
This work was supported by EPSRC grant EP/N031768/1 (POETS project).