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The Janus triad: Exploiting parallelism through dynamic binary modification

Accepted version
Peer-reviewed

Type

Conference Object

Change log

Authors

Zhou, R 
Wort, G 
Erdős, M 
Jones, TM 

Abstract

We present a unified approach for exploiting thread-level, data-level, and memory-level parallelism through a same-ISA dynamic binary modifier guided by static binary analysis. A static binary analyser first examines an executable and determines the operations required to extract parallelism at runtime, encoding them as a series of rewrite rules that a dynamic binary modifier uses to perform binary transformation. We demonstrate this framework by exploiting three different kinds of parallelism to perform automatic vectorisation, software prefetching, and automatic parallelisation together on legacy application binaries. Software prefetch insertion alone achieves an average speedup of 1.2×, comparing favourably with an automatic compiler pass. Automatic vectorisation brings speedups of 2.7× on the TSVC benchmarks, significantly beating a compiler approach for some workloads. Finally, combining prefetching, vectorisation, and parallelisation realises a speedup of 3.8× on a representative application loop.

Description

Keywords

33 Built Environment and Design, 3301 Architecture

Journal Title

VEE 2019 - Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

Conference Name

VEE '19: 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments

Journal ISSN

Volume Title

Publisher

ACM
Sponsorship
Engineering and Physical Sciences Research Council (EP/K026399/1)
Engineering and Physical Sciences Research Council (EP/P020011/1)
Engineering and Physical Sciences Research Council (EP/N509620/1)