TFT’s Circuit Simulation Models and
Analogue Building Block Designs
Xiang Cheng
Department of Engineering
University of Cambridge
This dissertation is submitted for the degree of
Doctor of Philosophy
Homerton College February 2018

I would like to dedicate this thesis to my loving parents
and my beautiful and considerate wife . . .

Acknowledgements
I would like to express my deep sense of gratitude to my supervisor Prof. Arokia Nathan,
who gave me the opportunity to study in one of the most known universities in the world.
He is not only a brilliant supervisor who provides sufficient guidance, knowledge and care,
but also a very nice person who treats students like family members. The dissertation could
not be finished without his help especially in its scope and vision. The flexible group culture
gives us sufficient time and space to think deeply about research and life, which I surely
benefit a lot from.
Secondly, I would also like to thank my parents for their caring and support during the
years. As the single child of the family, I am always overwhelmed by the care and support
they have given to me. Now it is approaching the end of my PhD study and I have started
my own family. Living on my own does make me understand more of your words and the
emotions under your tongue, this could only make me feel more appreciated for your care
and support. I would like to thank my wife Rui Mo. A lot has happened between us and our
lives during this 4 years. We were boyfriend and girlfriend and now we are husband and
wife. We were both students when we arrive in UK and now we are both doctors. It is very
fortunate for me to have you around my life. I cannot finish the dissertation at least to the
same quality without your support and I certainly would not live as well.
Many thanks to Dr. Sungsik Lee, whom I worked close together with. It has been a very
nice time chatting, drinking and smoking (although I only smoke second-hand) together. He
has given me many valuable advice in research from the very detail like drawing figures to
the general question as what is a valuable research. A great portion of this dissertation has
been influenced by him. More importantly, the discussions has helped me a lot regarding
how to conduct research and how to distinguish the value of research from industry.
I would like to thank Shuo Gao for the accompany of sitting next to me through out the 4
years study. It’s been great discussing with him mostly everything about life and research.
Although we were working on different topics, the general discussions really keeps me
thinking. Also his productiveness also pushes me to publish papers more efficiently in these
years.
vi
Thanks to Jiahao Li and Dr. Hanbin Ma for the supervision and help on the bio-sensor
project. Although it is a separate project from this thesis, it broadens my knowledge on the
bio-sensing applications. Believe it or not, bio-sensing was intended to be one application
example of this thesis. However, I later decided to delete the part due to the very different
technology it was used in the bio-sensing project.
Thanks to Guangyu Yao and Chen Jiang for doing the processing in the group. The hard
working of both of you always pushes me forward. Thanks to Constantinos Tsangarides
for the discussions for several side projects and the trust of me answering several of your
difficult questions. I would also like to thank him for his patient explanation of religious
stories which, as a Chinese, I’ve never heard much of. Thanks to Mojtaba Bagheri for the
discussion over the AMOLED pixel project. There were several points that you have taught
me which I would otherwise not know.
Many thanks to Cambridge Commonwealth, European & International Trust and Chinese
Scholarship Council for providing the scholarship.
Abstract
Building functional thin-film-transistor (TFT) circuits is crucial for applications such as
wearable, implantable and transparent electronics. Therefore, developing a compact model of
an emerging semiconductor material for accurate circuit simulation is the most fundamental
requirement for circuit design. Further, unique analogue building blocks are needed due to
the specific properties and non-idealities of TFTs.
This dissertation reviews the major developments in thin-film transistor (TFT) modelling
for the computer-aided design (CAD) and simulation of circuits and systems. Following the
progress in recent years on oxide TFTs, we have successfully developed a Verilog-AMS
model called the CAMCAS model, which supports computer-aided circuit simulation of
oxide-TFTs, with the potential to be extended to other types of TFT technology families.
For analogue applications, an accurate small signal model for thin film transistors (TFTs)
is presented taking into account non-idealities such as contact resistance, parasitic capaci-
tance, and threshold voltage shift to exhibit higher accuracy in comparison with the adapted
CMOS model. The model is used to extract the zeros and poles of the frequency response in
analogue circuits.
In particular, we consider the importance of device-circuit interactions (DCI) when
designing thin film transistor circuits and systems and subsequently examine temperature-
and process-induced variations and propose a way to evaluate the maximum achievable
intrinsic performance of the TFT. This is aimed at determining when DCI becomes crucial
for a specific application. Compensation methods are reviewed to show examples of how
DCI is considered in the design of AMOLED displays.
Based on these design considerations, analogue building blocks including voltage and
current references and differential amplifier stages have been designed to expand the analogue
library specifically for TFT circuit design. The VT shift problem has been compensated based
on unique circuit structures.
For a future generation of application, where ultra low power consumption is a critical
requirement, we investigate the TFT’s subthreshold operation through examining several
figures of merit including intrinsic gain (Ai), transconductance efficiency (gm/IDS) and cut-off
frequency ( fT ). Here, we consider design sensitivity for biasing circuitry and the impact of
device variations on low power circuit behaviour.

Table of Contents
List of Figures xiii
List of Tables xvii
Nomenclature xix
1 Introduction 1
1.1 Thin-Film Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 TFT Enabled Flexible and Transparent Electronics . . . . . . . . . . . . . 3
1.3 Research Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 TFT Compact Modelling 7
2.1 Computer Aided Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Physical and Empirical Modelling . . . . . . . . . . . . . . . . . . 8
2.2 Cambridge’s TFT Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 Above-Threshold Model . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.2 Subthreshold Model . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3 Off Region Model . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.4 Unified Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3 Computer Interpretation of Device Model . . . . . . . . . . . . . . . . . . 20
2.3.1 SPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.2 Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.3 Short Summary of Comparison . . . . . . . . . . . . . . . . . . . 24
2.4 CAMCAS Model in Simulation Environment . . . . . . . . . . . . . . . . 25
2.5 Summary and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 Small Signal Modelling 29
3.1 General Small Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
x Table of Contents
3.1.1 Midband Small Signal Model . . . . . . . . . . . . . . . . . . . . 29
3.1.2 High-Frequency Small Signal Model . . . . . . . . . . . . . . . . 31
3.2 TFT Small Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.1 Midband TFT Model . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2.2 High-Frequency TFT Model . . . . . . . . . . . . . . . . . . . . . 38
3.3 Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3.2 s-parameters and fT Measurement . . . . . . . . . . . . . . . . . . 42
3.3.3 fT and VT shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.4 Summary and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4 TFT analogue circuit building blocks 63
4.1 Status of TFT Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2 Challenges of TFT Analogue Circuits . . . . . . . . . . . . . . . . . . . . 63
4.3 Building Blocks and Simulations . . . . . . . . . . . . . . . . . . . . . . . 65
4.3.1 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.3.2 Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.3.3 Current Reference . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.3.4 Differential Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 76
4.4 Full Op-Amp Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.5 Current Mirror Layout and Measurement . . . . . . . . . . . . . . . . . . . 78
4.6 Summary and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5 Conclusion and Future Work 85
References 87
Appendix A Device Circuit Interaction 99
A.1 Importance of DCI in TFTs . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.2 Impact of TFT Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
A.2.1 Temperature Dependence . . . . . . . . . . . . . . . . . . . . . . . 100
A.2.2 Geometric Dependence . . . . . . . . . . . . . . . . . . . . . . . . 104
A.3 Compensation Methods in Circuits & Applications . . . . . . . . . . . . . 107
A.3.1 On-Pixel Programming . . . . . . . . . . . . . . . . . . . . . . . . 108
A.3.2 Off-Pixel Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . 108
A.4 Specific Device Properties and Alternate Circuit Architecture . . . . . . . . 112
A.4.1 Analogue Gain Stage with Mono-type TFTs . . . . . . . . . . . . . 112
Table of Contents xi
A.4.2 Persistent Photoconductivity . . . . . . . . . . . . . . . . . . . . . 115
A.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Appendix B Subthreshold Operation for Schottky Barrier TFTs 119
B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
B.2 Subthreshold Model for IGZO TFTs . . . . . . . . . . . . . . . . . . . . . 120
B.2.1 DC Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
B.2.2 Small Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . 120
B.3 Figures of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
B.3.1 Intrinsic Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
B.3.2 Transconductance Efficiency . . . . . . . . . . . . . . . . . . . . . 122
B.3.3 Cut-off frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
B.4 Sensitivity to Variations and Bias . . . . . . . . . . . . . . . . . . . . . . . 125
B.4.1 Current Sensitivity to Variations . . . . . . . . . . . . . . . . . . . 125
B.4.2 Accuracy Requirement for Biasing Circuitry . . . . . . . . . . . . 127
B.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

List of Figures
1.1 Conceptual structure of a bottom-gate TFT. . . . . . . . . . . . . . . . . . 2
1.2 Field effect mobility and stage delay for different semiconductor families.
Captured from [? ]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Flexible circuits and displays with TFTs (a) stress sensor array with built-in
amplifiers (b) Σ−∆ ADC (c) op-amp (d-f) flexible and transparent displays.
Figures are captured from [? ? ? ? ? ? ]. . . . . . . . . . . . . . . . . . . . 4
2.1 Carrier transport combining percolation with trap-limited conduction (TLC)
for oxide semiconductor TFTs (Here, DB and WB denote spatial distance and
width of potential barriers, respectively) . . . . . . . . . . . . . . . . . . . 9
2.2 Comparison between measured and modelled transfer characteristics (IDS
vs. VGS) for the above-threshold region. For each region, a good agreement
between measurement and modelling is achieved. . . . . . . . . . . . . . . 12
2.3 Comparison between measured and modelled transfer characteristics at dif-
ferent temperatures. Here, the proposed model shows a better agreement
compared to the conventional model (e.g. trap-limited conduction model). . 13
2.4 Density of states profile with (a) Fermi level within interface states at low
gate voltage, and (b) the case of deep states dominant with increasing gate
voltage corresponding Fermi level now within deep states. . . . . . . . . . 14
2.5 Measured and modelled subthreshold current (Isub) as a function of VGS . . 15
2.6 Measured and modeled IDS vs. VGS at subthreshold region for a different
VDS. Inset: Measured and modeled IDS vs. VDS for VGS = 0.5V . Here, the
equation is simplified from Eq. (2.5) introducing the pre-constant I0 which is
around 10pA at VGS = 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7 (a) Calculated IDS vs. VX of the combined above- and sub-threshold model for
different VG (4, 6, 8V). (b) First, (c) second, (d) third, and (e) fourth deriva-
tives of IDS with respect to VX . The inset of (a): test circuit configuration of
the GST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
xiv List of Figures
2.8 (a) Schematic IDS vs. VGS curves (gray circles) with the conventional power-
law models for subthreshold (Sub-T, solid line) and above-threshold (Above-
T, dot line) characteristics. In this case, we need two models for these two
different operational regions. Here, Von and VT are on-voltage and threshold
voltage, respectively. (b) Schematic IDS vs. VGS curves (gray circles) with
only one model: unified model which can cover subthreshold as well as
above-threshold regions at the same time. . . . . . . . . . . . . . . . . . . 19
2.9 Parameter extraction for unified model & measured and modelled transfer
curve with percentage error . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.10 Verilog-A behaviour model in early mixed signal simulation environment . 23
2.11 Verilog-A(MS) extension for compact modelling with SPICE like simulator
integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.12 Circuit design and simulation flow using CAMCAS model in Cadence Design
Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.13 A voltage amplifier used in simulation with CAMCAS model . . . . . . . . 26
2.14 Simulation results of the voltage amplifier . . . . . . . . . . . . . . . . . . 27
3.1 Small signal model for a general 3 terminal device . . . . . . . . . . . . . . 31
3.2 High frequency small signal models for CMOS and BJT . . . . . . . . . . 32
3.3 The inner structure based on which static TFT models are developed . . . . 34
3.4 Midband small signal models . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5 Midband TFT model considering VT shift . . . . . . . . . . . . . . . . . . 38
3.6 Bottom-gate TFT structure considering passive components of the small
signal equivalent circuit. COV S and COV D are the overlap capacitance at
source and drain side; Cch is the channel capacitance; RS and RD are the
contact resistances at source and drain side. . . . . . . . . . . . . . . . . . 39
3.7 High frequency small signal models . . . . . . . . . . . . . . . . . . . . . 39
3.8 Measurement setup for fT and s-parameters . . . . . . . . . . . . . . . . . 42
3.9 I-V characteristic of the TFT under test . . . . . . . . . . . . . . . . . . . 43
3.10 Comparison between terms of (1−S11)(1+S22) and S12S21 . . . . . . . . 45
3.11 Comparison between Eq. (3.20) and its approximation Eq. (3.21) . . . . . . 46
3.12 Equivalent circuit for S11 and S21 measurement . . . . . . . . . . . . . . . 47
3.13 Magnitude and phase measurement and simulation for S11 parameter based
on TFT model and adapted CMOS model . . . . . . . . . . . . . . . . . . 48
3.14 S11 simulation of the TFT and CMOS models . . . . . . . . . . . . . . . . 50
3.15 Magnitude and phase measurement and simulation for S21 parameter based
on TFT model and adapted CMOS model . . . . . . . . . . . . . . . . . . 52
List of Figures xv
3.16 S11 simulation of the TFT and CMOS models . . . . . . . . . . . . . . . . 54
3.17 Magnitude and phase measurement and fitting for S11 parameter based on
single pole and zero approximation . . . . . . . . . . . . . . . . . . . . . . 57
3.18 h21 results with and without S11 fitting . . . . . . . . . . . . . . . . . . . . 58
3.19 S21 measurement showing low frequency range for gm extraction . . . . . . 59
3.20 fT vs. gm relation through S-parameter measurement . . . . . . . . . . . . 60
3.21 gm vs. VT shift relation through stress measurement with I-V sweep . . . . 60
3.22 Extracted ∆ fT vs. VT shift relation. The error bar here is the standard
deviation of the fitting to obtain the corresponding result. . . . . . . . . . . 61
4.1 Voltage reference circuit with all TFTs working in saturation region . . . . 66
4.2 Simulation results for the proposed voltage reference circuit with two differ-
ent values of β1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.3 Pseudo p-type current designed with all n-type TFTs . . . . . . . . . . . . 68
4.4 Simulation results of the proposed pseudo p-type current mirror . . . . . . 70
4.5 Fully n-type current reference circuit with pseudo p-type current mirror and
a reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.6 Simulation results of the current reference circuit with resistor where W3,4
are simulated with different value to exhibt the change of working range . . 72
4.7 Fully n-type current reference circuit without resistor . . . . . . . . . . . . 73
4.8 Simulation results of the current reference circuit without resistor where WR
is simulated with different value to exhibt the change of output current . . . 74
4.9 Improved current reference circuit with negative feedback on TR . . . . . . 75
4.10 Simulation results of the improved current reference circuit where WR is
simulated with different value to exhibt the change of output current . . . . 75
4.11 Differential amplifier stage with pseudo p-type mirror . . . . . . . . . . . . 76
4.12 Simulation results of the proposed differential amplifier stage . . . . . . . . 77
4.13 Full op-amp design with supply independent bias . . . . . . . . . . . . . . 78
4.14 Simulation results of the proposed op-amp . . . . . . . . . . . . . . . . . . 79
4.15 Schematic of the fabricated ISO current mirror. . . . . . . . . . . . . . . . 80
4.16 Picture and measurement result of the fabricated current mirror based on a
separate-device layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.17 Picture and measurement result of the fabricated current mirror based on a
interdigitated stacked layout. . . . . . . . . . . . . . . . . . . . . . . . . . 82
A.1 Illustration of DCI in relation to performance requirements of a desired
application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
xvi List of Figures
A.2 I-V characteristics of the examined TFT under different temperatures . . . . 101
A.3 Extracted values of K, αp and VT at the different temperatures . . . . . . . 103
A.4 Normalized temperature sensitivity of current and the contribution of differ-
ent parameters at 313K . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
A.5 Fitted probability distribution and histogram of the three key parameters. The
data was extracted at room temperature from a 1080*1920 RGBW AMOLED
panel with pixel circuits as described in Fig. A.7. . . . . . . . . . . . . . . 106
A.6 Normalized standard deviation of current and the contribution of different
parameters(K, VT and α) . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.7 AMOLED pixel structure for off-pixel defect extraction and feedback . . . 109
A.8 Equivalent circuit for the defect extraction phase of OLED and TFT . . . . 110
A.9 Extracted aging parameters for (a) TFTs and (b) OLEDs after continuously
displaying a checker board (W: displayed with white squares, B: displayed
with black squares) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A.10 Extracted aging parameters for (a) TFTs and (b) OLEDs after continuously
displaying a checker board (W: displayed with white squares, B: displayed
with black squares) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A.11 (a) Common-source gain stage of an amplifier (b) sketch of different type of
loads passing through the same bias point . . . . . . . . . . . . . . . . . . 113
A.12 Gain stage of an amplifier with (a) feedback load (b) boost strap load . . . . 114
A.13 Band diagram to explain the effect of positive gate pulse on recovery. . . . 116
A.14 Persistent photoconductivity (PPC) and its removal . . . . . . . . . . . . . 117
B.1 Simulation result for the intrinsic gain (Ai) of the Schottky-Barrier IGZO TFT
(SB-TFT). The parameter n is the ideality factor of the source-semiconductor
junction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
B.2 gm/IDS from deep subthreshold to above threshold region. The value reaches
maximum at deep subthreshold and increases with steeper SS. . . . . . . . 123
B.3 Cut-off frequency vs. voltage bias for different SS. . . . . . . . . . . . . . 124
B.4 Normalized sensitivity to VT shift for different SS . . . . . . . . . . . . . . 125
B.5 Normalized sensitivity to SS variations for different SS mean values . . . . 126
B.6 The useful bias range for a depletion load common-source amplifier. (a) con-
ceptual figure of the load line and transfer curve of the amplifier, where green
curve illustrates the correct bias condition and blue curves illustrates that the
amplifying TFT is biased out of useful bias range (b) circuit schematic of
the amplifier (c) simulated useful bias range with respect to SS . . . . . . . 127
List of Tables
2.1 Extracted Subthreshold Parameters at T=300K . . . . . . . . . . . . . . . . 16
2.2 Extracted Parameters for Unified Model at T=300K . . . . . . . . . . . . . 20
2.3 Comparison between different model languages . . . . . . . . . . . . . . . 24
3.1 Summary of parameters for the CMOS and TFT models . . . . . . . . . . . 62

Chapter 1
Introduction
The wide usage of amorphous silicon (a-Si:H) thin film transistors (TFT) in TFT-LCD display
[? ] which dates back to the 1980s has boosted research on materials and the processing
technology of TFTs [? ? ], and has subsequently enables another success in organic displays
[? ].
Further improvements in TFT device performances and its flexibility, transparency, roll-
to-roll compatibility and low cost make them promising in many other applications such as
radio-frequency identification (RFID) tags [? ], sensors [? ] and wearable devices. In order
to reduce the integration complexity and system cost, a system-on-panel approach has been
pointed out aiming at producing all kinds of circuit building blocks on a single substrate [? ].
Although circuit blocks such as logic gates [? ], amplifiers [? ] and analogue-to-digital
coverters (ADCs) [? ] have been reported in recent years, the capability of TFT circuits is
still low. Complex systems with only TFTs are still lacking, especially for TFT analogue
circuits and applications. The reasons are various. Firstly, due to the ever-changing nature
of the semiconductors used in newly developed TFT technologies, device models can vary
because of changes in the underlying physics. However, an accurate model for newly
developed technology is essential for circuit design. Secondly, the design flexibility of TFTs
is not comparable with the well-developed silicon metal–oxide–semiconductor field-effect
transistors (MOSFET) or even bipolar junction transistors (BJTs). Lacking complementary
semiconductors and the capability of making enhancement and depletion TFTs on the same
substrate, many existing circuit blocks are not directly usable thus limiting the flexibility of
designing TFT circuits.
Therefore, the dissertation as a whole is dedicated to exploring and synthesising a
more accurate model specifically for circuit simulation along with development of essential
building blocks for analogue circuits so as to build a bridge between the existing circuit
topologies to the TFT domain.
2 Introduction
Fig. 1.1 Conceptual structure of a bottom-gate TFT.
1.1 Thin-Film Transistors
It is surprising to find out that the first concept of the thin film transistor dates back to the
1930s, even before the first point contact transistor was demonstrated. The early failure of the
attempt to make TFT devices and the later success of the crystalline silicon devices lead to
an abandonment of the TFT concept in the industry until a killer application was identified,
i.e. the TFT-LCD, in the 1980s [? ]. Extensive research on different materials started from
then on.
The TFT by definition is “a field effect transistor made of nonsingle crystal semicon-
ductor film deposited on an insulating substrate”, quoting the definition used in [? ]. A
conceptual figure of a TFT structure is shown in Fig. 1.1 where a bottom-gate structure
is used. The device is designed following the same principle as other field effect transis-
tors. The rule of thumb is that under working conditions, the vertical electric field through
semiconductor is much higher than the horizontal electric field along the surface of the semi-
conductor. Therefore, the gate electrode can have dominating control over the semiconductor
characteristics.
By virtue of its working principle, a TFT is the same as a floating body MOSFET. How-
ever, as semiconductors used in these devices are normally amorphous or poly-crystalline,
the effective mobility if much lower than single crystal silicon in MOSFETs, yielding a much
lower operating current. This motivates researchers to improve the effective mobility of TFTs
in subsequent years.
1.2 TFT Enabled Flexible and Transparent Electronics 3
Fig. 1.2 Field effect mobility and stage delay for different semiconductor families. Captured
from [? ].
Up until now, many alternative materials have been found to exhibit higher or comparable
effective mobility against the first widely used TFT technology which is based on a-Si.
Fig. 1.2 lists the mobility achieved in a range of different semiconductor materials [? ].
Among the materials listed in Fig. 1.2, metal-oxide semiconductors stand out as the
potential leading semiconductor material for TFTs as they exhibit high mobility and good
uniformity in large scale and amenable to low-temperature fabrication. In addition, metal
oxide semiconductors are very promising for transparent and flexible electronics due to their
wide bandgap. Therefore, it will be used as the main consideration in developing the models
and circuit blocks in this dissertation.
1.2 TFT Enabled Flexible and Transparent Electronics
The low processing temperature of TFT technologies such as a-Si:H, metal oxide and organic
TFTs has made them compatible with several flexible substrates, for example, plastic or paper
substrates. This directly makes large-area, low cost, roll-to-roll, transparent and flexible
systems promising [? ]. Prototypes of flexible displays, digital circuits and amplifiers have
been reported in recent years demonstrating the possibility of realising modern electronics in
a different and flexible manner [? ? ? ? ? ? ]. Several examples are shown in Fig. 1.3.
Another promising approach for flexible electronics lies in healthcare. Lower power
consumptions is a critical requirement in health care monitoring systems especially when
4 Introduction
Fig. 1.3 Flexible circuits and displays with TFTs (a) stress sensor array with built-in amplifiers
(b) Σ−∆ ADC (c) op-amp (d-f) flexible and transparent displays. Figures are captured from
[? ? ? ? ? ? ].
continuous monitoring is needed in daily life, and in implantable applications where long
lifetime is of concern. As TFTs are generally working at a lower current level compared
with silicon MOSFET technology, they are naturally more suited for low power applications.
Recent research has reported that ultra-low power working (<1nW) is possible [? ] when
biasing TFTs in the subthreshold region, which could potentially lead to battery-less systems.
It is worth mentioning that although many prototype applications have been demonstrated,
building a full system on a flexible substrate is still very challenging as in most applications,
rigid crystalline silicon-based integrated circuits or components are still needed in biasing
and operating the TFT circuits, which are not currently replaceable with TFT circuits.
1.3 Research Goals
To enable various functionalities efficiently, TFT circuit designs and simulations are indis-
pensable. However, the simulation platforms for newly emerging technologies are not readily
available. For a-Si TFTs, the well-known RPI model [? ] has become a commercial standard
supported by many simulation platforms including SmartSpice, HSPICE, Spectre, etc where
designers can easily simulate various circuits with adequate accuracy.
However, as a newly emerging technology, no computer-aided design (CAD) tool for
metal-oxide TFTs has yet become a standard despite the improved performances compared
with a-Si. In order to accurately simulate circuits and design various functions with metal
oxide TFTs, we need to first investigate both the static and dynamic models in a simulation en-
1.4 Thesis Organization 5
vironment. Subsequently, building blocks at the bottom level should be engineered to connect
TFT designs with the well-researched silicon complementary metal-oxide-semiconductor
(CMOS) circuit and systems.
Therefore the main goal of the dissertation is as follows:
1. Investigate compact modelling for circuit simulations.
2. Investigate linear models for design simplicity, and develop an accurate small signal
model specifically for TFTs.
3. Design building blocks for bottom level analogue circuits in order to build a bridge
between the TFT circuit design with the well studied CMOS designs.
1.4 Thesis Organization
The dissertation includes 5 chapters and 2 appendices. This first chapter introduces the
background and the motivation of the research and explains the main goal of this research.
Chapter 2 mainly reviews the CAMCAS model developed in Cambridge where a lot of work
has been completed from previous efforts. Chapter 3 investigates the widely used CMOS
small signal model and the inadequacy of its application in TFTs. A new model is developed
taking into consideration of non-idealities in TFT devices. In Chapter 4, several building
blocks for analogue circuits are designed and simulated with the CAMCAS model. The
design of a supply independent op-amp is presented. Chapter 5 concludes this dissertation
and discusses possible extensions of this research.
The two appendices discuss the device circuit interaction (DCI) and subthreshold circuit
possibilities of TFT devices. In particular Appendix A considers DCI that happens in TFT
circuit designs and available approaches are reviewed. Thermal and geometric variations are
measured and the effects on simple analogue circuit performance are analysed. Based on the
knowledge developed in the above chapters, Appendix B evaluates the analogue performance
and the design difficulties in the newly proposed way of biasing Schottky-barrier TFTs in
subthreshold region, which extends the subthreshold modelling of Chapter 2.

Chapter 2
TFT Compact Modelling
2.1 Computer Aided Design
The growing maturity of thin film transistor (TFT) technology coupled with newly emerging
materials and processes are enabling integration of circuits and systems for a new family of
applications ranging from biosensing systems to areas augmenting displays and imaging [?
? ? ? ]. The design of systems places great demand for fast computer aided design (CAD)
tools to accurately and reliably predict system behaviour.
CAD always requires accuracy, high speed and reliable convergence of device models. In
order to achieve high accuracy in all working regions without use of many fitting parameters,
a good understanding of device physics is needed. However, physical models are not
necessarily sufficient for good CAD in the sense that the equations could be complex, which
can lead to slow execution or convergence problems. Therefore, simplification of the model
equations without sacrificing accuracy is one of the major requirements for a good CAD
model. In addition, the model should be adaptive to a wide range of technological/process
parameters through simple extraction procedures.
During the past 30 years, a great amount of effort has been made in the TFT modelling
area for various semiconductor technologies, including amorphous silicon [? ? ? ? ? ? ?
], polysilicon [? ], organics [? ? ? ? ? ] and metal oxides [? ? ? ? ? ? ? ]. For a-Si
TFTs, several SPICE models have been developed. Specifically, the model developed by
Rensselaer Polytechnic Institute, also known as the RPI model [? ], has become a commercial
standard supported by many simulation platforms including SmartSpice, HSPICE, Spectre,
etc. However, no CAD tool for organic and metal-oxide TFTs has yet become a standard due
to the rapid evolution of materials and device structures.
In this chapter, we will review the major contributions to the TFT modelling area and
compare the differences between Verilog-AMS and SPICE from the standpoint of compact
8 TFT Compact Modelling
device modelling. Finally, we present the implementation of the Cambridge TFT compact
model [? ] for oxide TFTs in Verilog-AMS for Spectre simulation. The major goal of
this review is to give the reader guidelines for implementing device models for the CAD of
circuits and systems.
2.1.1 Physical and Empirical Modelling
Physical and empirical modelling approaches are generally aimed at providing an accurate
model for a given transistor or transistor family, which covers all working regions of the
device. While the major consideration is accuracy, the developed model is not necessarily
physical. In this sense, it is theoretically possible to use polynomial approximation or other
empirical ways to fit any kind of transistor behaviour with acceptable accuracy. However,
without a proper understanding of the underlying device physics, the resulting number of
fitting parameters could be large and difficult to extract from measurements since the model
should cover a wide range of different bias conditions and transistor scales. Therefore, the
transistor models used in a simulator are often a combination of terms and coefficients that
are physically and empirically based.
Recent efforts have primarily focused on physically-based approaches in an attempt to
develop simple and accurate models. The most well-studied material for TFTs is amorphous
silicon (a-Si:H). Several models have been developed based on different distributions of deep
states and tail states of the semiconductor to describe static and dynamic behaviour for the
above and subthreshold regions [? ? ? ]. Other properties including trap related VT shift [? ]
and the off/leakage currents [? ]. The RPI model [? ] captures most of the device properties
leading to satisfactory simulation results and thus has been widely used.
For organic TFTs, researchers have developed models based on multiple trapping and
release (i.e. trap-limited conduction) [? ] and variable range hopping (VRH) [? ? ? ].
However, due to the diverse use of materials in the TFT, the underlying physics differs, and
therefore a trend has emerged to develop a model that is unified but less physical [? ].
As for metal oxide TFTs, modelling efforts are still in their infancy, although there are
growing interests in the area for implementation of circuits and systems. In what follows,
early efforts in compact models for CAD of oxide TFTs are reviewed.
2.2 Cambridge’s TFT Models
Compared with a-Si TFTs, the oxide system has unique properties, which need to be captured.
For example, localised traps or band tail states in oxides do not exist to the same extent as
2.2 Cambridge’s TFT Models 9
Fig. 2.1 Carrier transport combining percolation with trap-limited conduction (TLC) for
oxide semiconductor TFTs (Here, DB and WB denote spatial distance and width of potential
barriers, respectively)
a-Si [? ]. Their tail state density is much lower and hence trap-limited conduction is generally
insignificant [? ? ]. In addition, more complex systems such as amorphous indium gallium
zinc oxide (a-IGZO) can have compositional disorder due to the random distribution of metal
constituents [? ? ]. This gives rise to potential barriers above the conduction band minima
(Em), suggesting the presence of percolation conduction [? ? ? ].
In the following, compact models for the terminal current-voltage behaviour are presented
taking into account the different transport mechanisms in the device for the above- and sub-
threshold regions of TFT operation. The former is based on a mobility model that combines
trap-limited conduction (TLC) with percolation conduction. The latter takes into account
diffusion and drift current components [? ]. A unified model is then presented that covers
both regions based on a single expression that uses a reference turn-on voltage Von rather
than VT [? ]. Good agreement with measured terminal characteristics is obtained over the
entire range of gate-source voltage (VGS) > Von for the test TFTs with an a-IGZO channel.
2.2.1 Above-Threshold Model
As illustrated in Fig. 2.1, oxide TFTs have potential barriers above Em due to compositional
disorder, suggesting percolation conduction when electrons are released into the conduction
band. Moreover, there are localised tail states within the gap states, implying trap-limited
conduction. In particular, oxide semiconductors can have a shallow slope of the tail states
(kTt) ∼ 20meV , smaller than the thermal energy (kT ) at 300K, leading to different mobility
behaviour. This suggests that the field effect mobility (µFE) model needs to be modelled
based on TLC and percolation conduction, although the former is not as significant as
compared to a-Si.
10 TFT Compact Modelling
1. Trap-limited conduction (TLC)
Effect of trap-limited conduction (TLC) can be considered as µFE being proportional
to ratio (γT LC) of free carrier density (n f ree) and trapped carrier density (ntrap), yield-
ing γT LC = n f ree/(n f ree + ntrap). Here, n f ree = NCexp[(EF −Em)/kT ], where NC is
effective density of states in conduction band and kT the thermal energy. And the
expression for ntrap is approximated with kTt < kT using exponential distribution of
tail states. This yields ntrap = NtckTtexp[(EF −Em)/kT ], where Ntc is the density of
trap states at conduction band edge. Now, we have γT LC as just a constant,
γT LC ≡ n f ree
(n f ree+ntail)
≈ NC
NC +NtckTt
(2.1)
2. Percolation Conduction
Percolation conduction associated with potential barriers above Em can be consid-
ered as mobility scaled from band mobility (µ0), assuming Gaussian random dis-
tribution of potential barriers with the mean (φB0) and the variance (σB0). This
yields µ∗0 = µ0exp[−qφB0/kT +(qσB0)2/(kT )2]. Here, φB0 can be reduced by ∆φB0
due to thermally released electrons, depending on Fermi level change (∆EF ), as
described in Fig. 2.1. The thermally reduced barrier height can be expressed as
φB0exp(−γB∆EF/kT ), where γB ≡ (DB−WB)/DB, which can be approximated as
φB0(1− γB∆EF/kT ) when γB∆EF/kT << 1 by Taylor expansion. Thus, ∆φB0 is de-
fined as γB∆EF/kTφB0. These conditions yield the percolation mobility (µPer) as
follows,
µPer ≡ µ0exp
(
−q(φB0−∆φB)
kT
+
(qσB0)2
2(kT )2
)
= µ∗0 exp
(
γB∆EF
kT
φB0
) (2.2)
where µ∗0 = µ0exp[−qφB0/kT + (qσB0)2/2(kT )2] considered as an effective band
mobility.
3. Combined Mobility Model with VGS dependence
In Eq. (2.2), the ∆EF is controlled by gate voltage (VGS). The relationship between them
can be derived by solving Poisson’s equation, yielding ∆EF = 2(kT/q)ln[Cox(VGS−
VT )/Qre f ], where Cox is gate-insulator capacitance, VT threshold voltage, and Qre f ≡
{2εSNCkTexp[(EF0−Em)/kT ]}0.5. Combining TLC with percolation from Eqs. (2.1)
to (2.2), we now have the VGS dependent mobility relation,
2.2 Cambridge’s TFT Models 11
µFE ≡ µPerγT LC = µ∗0
(
NC
NC +NtckTt
)(
Cox
Qre f
)αp
(VGS−VT )αp (2.3)
As can be seen, Eq. (2.3) follows a power law. Here, αp ≡ 2qφB0γB/kT , related
to percolation. In Eq. (2.3), TLC affects the constant term, while the exponent is
determined by percolation.
4. Current-Voltage Relation
With Eq. (2.3) and the definition of drift current: IDS = µFECox(VGS−VT−Vch)dVch/dx,
current-voltage relation IDS(VGS) can be derived with the integral ranges: x=0 to L and
channel potential (Vch) = 0 to VDS,
IDS ≡ µ∗0
(
NC
NC +NtckTt
)
W
L′
Cαp+1ox
Qαpre f
(VGS−VT )αp+1V ′DS (2.4)
In Eq. (2.4), L′ is defined as L−∆L, where ∆L is effective channel length reduction,
and effective drain voltage V ′DS =VDS−2RCIDS, where RC is contact resistance. For
saturation region expression, Eq. (2.4) can be reformed with a saturation parameter
(βsat), replacing V ′DS by βsat(VGS−VT ). Fig. 2.2a shows a comparison between mea-
sured and modelled transfer characteristics (IDS vs. VGS) at VDS = 0.1V , providing a
good agreement. The measured saturation characteristics at VDS = 20V is also well
matched with the modelled results, as seen in Fig. 2.2b.
To check the model validity for temperature dependency, we measured and simulated
the drain current as a function of gate bias for different temperatures, e.g. 100K, 200K, and
300K, respectively. As seen in Fig. 2.3a, there is good agreement between the measurements
and the model, Eq. (2.4). For purposes of validation, the modelled values of exponent (αp)
in the power-law, Eq. (2.4), are compared with the extracted values from the best fit since
it has a unique signature of percolation conduction, i.e. a = αp + 1 ≡ 2qφB0 · γB/kT + 1.
As seen in Fig. 2.3b, the proposed percolation model for φB0 · γB = 2.5meV shows better
agreement compared to the conventional model (e.g. trap-limited conduction model with
a = 2kTt/kT −1 for kTt = 30meV ).
2.2.2 Subthreshold Model
The subthreshold current in the limit of low VGS shows a linear dependence on VGS in a
semi-log plot, as illustrated in Fig. 2.6, suggesting diffusion current, as follows,
12 TFT Compact Modelling
(a) linear region with a small drain voltage (VDS) of 0.1V
(b) saturation region with a high VDS of 20V
Fig. 2.2 Comparison between measured and modelled transfer characteristics (IDS vs. VGS)
for the above-threshold region. For each region, a good agreement between measurement
and modelling is achieved.
2.2 Cambridge’s TFT Models 13
(a) Measured and modeled IDS-VGS for above-threshold region at VDS = 0.1V for different temperatures
(100K, 200K, 300K, respectively)
(b) Retrieved exponent (a) vs. temperature
Fig. 2.3 Comparison between measured and modelled transfer characteristics at different tem-
peratures. Here, the proposed model shows a better agreement compared to the conventional
model (e.g. trap-limited conduction model).
14 TFT Compact Modelling
Fig. 2.4 Density of states profile with (a) Fermi level within interface states at low gate
voltage, and (b) the case of deep states dominant with increasing gate voltage corresponding
Fermi level now within deep states.
IDi f f ≈ µ0 kTq
W
L′
Q f iexp
(
q
kT
(
VGS−VFB
1+q2Dit/Cox
))(
1− exp
(
−qV
′
DS
kT
))
(2.5)
where µ0 is the band mobility for electrons. Note that the subthreshold slope (SS) can be
derived from Eq. 2.5 with the definition dVGS/dlogIDS,
S≡ ln10kT
q
(
1+
q2Dit
Cox
)
(2.6)
As described in Fig. 2.4, interface states are occupied first, followed by filling deep states
located in the bulk at higher VGS. So, as the EF moves to the location of deep states for
increasing VGS, the drain current can be defined as a drift current (IDri f t),
IDri f t ≈ µ0WL′
Cαd+1ox
Qαdd
(VGS−VFB)αd+1V ′DS (2.7)
where Qd is a reference charge density associated with deep states, αd is power-law exponent
defined as 2(Td/T −1), and Td is the characteristic temperature of deep states.
We now have the current-voltage relations for both diffusion and drift components as
given by Eqs. (2.5) & (2.7). These equations can be combined as a total drain current (Isub)
in the subthreshold region using a harmonic average,
Isub ≡ (I−mDi f f + I−mDri f t)−1/m (2.8)
2.2 Cambridge’s TFT Models 15
(a) linear region with VDS = 0.1V
(b) saturation region with VDS = 20V
Fig. 2.5 Measured and modelled subthreshold current (Isub) as a function of VGS
16 TFT Compact Modelling
Table 2.1 Extracted Subthreshold Parameters at T=300K
Parameters Value
SS 0.19V/dec
Dit 1.64×1011cm−2eV−1
Io f f 2×10−14A
Q f i 7.05×10−14C/cm2
αd 2.26
Td 639K
Qd 7.8×10−8C/cm2
The examined TFT to verify this model, which is the same as that used in the previous
sections, has the following geometrical and physical parameters (extracted in the previous
sections): W = 100µm, L = 100µm, channel thickness tS = 40nm, channel permittivity
εS = 11.5ε0 (where ε0 is vacuum permittivity), VFB ∼ 0.6V , VT ∼ 4V , Cox = 11.5nF/cm2,
µ0 = 15cm2/V · s, and NC = 5×1018cm−3 at 300K. 2RC ≡ RSD = 9637Ω for W = 100µm
(equivalent to RSDW = 96.37Ω · cm) and ∆L = −3.5m (L′ = L−∆L = L+ 3.5µm). Other
extracted model parameters are summarized in Table 2.1. Fig. 2.5 shows the measured
subthreshold characteristics for a different VDS, providing a good agreement with each other.
To validate the subthreshold model in terms of the diffusion component in the examined
transistors, we measured the drain current for small VDS=0.01, 0.1, and 1V. Comparing to
the model, we get good agreement as seen in Fig. 2.6. In particular, as shown in the inset of
Fig. 2.6, the measured IDS vs. VDS at the diffusion dominant region of VGS (e.g. VGS = 0.5V)
is compared with the Eq. (2.5). Here, the dependence of the drain current on VDS is found to
follow the law of (1− exp(−qVDS/kT )) of Eq. (2.5) which is a signature of the presence of
the diffusion current.
Regarding continuity and symmetry of the compact model where above- and sub-
threshold models are combined, the model was subject to the Gummel symmetry test (GST)
[? ? ]. As seen in the inset of Fig. 2.7(a), VX represents a symmetrical voltage applied on
source and drain sides, respectively. Fig. 2.7 demonstrates perfect continuity and symmetry
as a function of VX even for the 4th derivative of IDS with respect to VX , suggesting it has
successfully passed the GST. For this, we employed smoothness and continuity functions for
the effective drain voltage and threshold voltage terms [? ].
2.2 Cambridge’s TFT Models 17
Fig. 2.6 Measured and modeled IDS vs. VGS at subthreshold region for a different VDS. Inset:
Measured and modeled IDS vs. VDS for VGS = 0.5V . Here, the equation is simplified from
Eq. (2.5) introducing the pre-constant I0 which is around 10pA at VGS = 0.5V.
2.2.3 Off Region Model
The off current can defined according to [? ] at VGS =VFB,
Io f f ≈ µ0 kTq
W
L′
Q f i
(
1− exp
(
−qV
′
DS
kT
))
(2.9)
2.2.4 Unified Model
As seen in the previous sections 2.2.1 & 2.2.2, the current-voltage relation needs to be derived
separately to describe the subthreshold and above-threshold characteristics. Here, we need
separate expressions for the subthreshold and above-threshold regions, implying two different
equation systems to describe total current (see Fig. 2.8). Moreover, in this case, threshold
voltage (VT ) is not immediately apparent from the I-V plot and needs to be extracted from
above-threshold region of the characteristic as a fitting parameter. However, the extracted
value of VT can be quite different depending on extraction method and the I-V data range
chosen for the fit. In contrast, turn-on-voltage (Von) is the gate voltage (VGS) at which drain
current (IDS) starts increasing rapidly, thus it is easy to identify Von on a semi-log plot of IDS
vs. VGS.
18 TFT Compact Modelling
Fig. 2.7 (a) Calculated IDS vs. VX of the combined above- and sub-threshold model for
different VG (4, 6, 8V). (b) First, (c) second, (d) third, and (e) fourth derivatives of IDS with
respect to VX . The inset of (a): test circuit configuration of the GST.
2.2 Cambridge’s TFT Models 19
Fig. 2.8 (a) Schematic IDS vs. VGS curves (gray circles) with the conventional power-
law models for subthreshold (Sub-T, solid line) and above-threshold (Above-T, dot line)
characteristics. In this case, we need two models for these two different operational regions.
Here, Von and VT are on-voltage and threshold voltage, respectively. (b) Schematic IDS vs.
VGS curves (gray circles) with only one model: unified model which can cover subthreshold
as well as above-threshold regions at the same time.
We can unify this to cover both subthreshold and above-threshold characteristics. The
proposed unified model is a single expression with a reference voltage level Von rather than
VT , providing good agreement with measured terminal characteristics over the entire range
of VGS >Von for the test TFTs with an amorphous InGaZnO (a-IGZO) channel, which is the
same TFT used in the previous sections. The derived equation for this model is as follows,
IDS = G0
W
L′
exp(κ(VGS−Von)α)V ′DS+ Io f f (2.10)
where G0 = µ0(εSkT NC)1/2, κ = ζ/2kT , and ζ & α are related to trap states. To extract the
values of κ and α , we can rewrite Eq. (2.10) as,
U ≡ I
′
DS/V
′
DS
d(I′DS/V
′
DS)/dVGS
=
1
ακ
(VGS−Von)1−α (2.11)
Here, I′DS ≡ IDS− Io f f . Therefore, 1−α and 1/(ακ) can be extracted from the plot of lnU
vs. ln(VGS−Von) as the slope and the intercept, respectively (as illustrated in Fig. 2.9a). The
extracted model parameters are summarized in Table 2.2.
Fig. 2.9b shows modelled results for different L (=25, 50, and 100µm), providing good
agreements with the measured characteristics. Also, they exhibit small average errors < 5%
over a wide range of VGS from 5 to 20V. Interestingly, the proposed model using only one
equation covers both the sub- and above-threshold regions at the same time. This is mainly
20 TFT Compact Modelling
Table 2.2 Extracted Parameters for Unified Model at T=300K
Parameters Value
G0 2.34×10−5ohm−1
κ −10.812V−α
α -0.675
due to a combination of the exponential function and power-law. Additional advantage of
this unified model is that it just needs a few model parameters to be implemented in model
code description, e.g. Veriog-A, thus providing a higher-speed simulation.
2.3 Computer Interpretation of Device Model
After having established an accurate analytical model for the TFT, computer implementation
for circuit simulation is not always easy. Several considerations including speed, convergence
and even the way of translating different form of equations into computer language should
be taken into consideration in this step.
For a-Si TFTs, several SPICE models have been developed. Specifically the model
developed by Rensselaer Polytechnic Institute, also known as the RPI model [? ], has become
a commercialized standard supported by many simulation platforms including SmartSpice,
HSPICE and Spectre, etc. However, CAD of organic and metal-oxide TFTs is yet to become
a standard due to the rapid and ongoing evolution in materials and device structures. In fact,
and as mentioned previously, there is a quest for unifying the TFT model to meet simulation
requirements of TFTs with ever changing structures and materials.
It is important to understand the benefits and drawbacks of SPICE and Verilog-A, while
developing a device model to be used in further circuit simulation and system design.
2.3.1 SPICE
SPICE is an open source analogue circuit simulation software firstly developed at the
University of California, Berkeley [? ]. The first two versions of this simulator was written
in Fortran. SPICE2 included several elements widely used in circuit simulation at that time,
including the diode, MOSFET, JFET and BJT, etc. In 1989, a version of the simulator
SPICE3 was re-written in C. This version includes the well-known BSIM model [? ].
Many commercial circuit simulators today are based on the aforementioned software
including PSPICE, HSPICE, SmartSpice, Spectre, etc. The fast simulation speed, high
accuracy and ease of use make the SPICE simulator extremely popular in the area of
2.3 Computer Interpretation of Device Model 21
(a) Plots of lnU vs. ln(VGS−Von). Here, linear fitting is applied over the entire range of ln(VGS−Von)
(b) Modeled results for different L in comparison with the measured curves using a unified model,
normalized error is illustrated in the inset.
Fig. 2.9 Parameter extraction for unified model & measured and modelled transfer curve with
percentage error
22 TFT Compact Modelling
circuit design. However, SPICE is written in a low level computer language (Fortran or
C) and so are the models used in it. Therefore, researchers should not only have a good
understanding of device physics but also need enough knowledge of the algorithms and
limitations of the simulator. The procedure for developing a stand-alone SPICE model (not
by combining existing elements) always takes time and resources. Due to the complexity of
model development in SPICE, currently only well developed and widely used devices are
having SPICE models.
It is worth noting that modern circuit simulators use a heavily modified original SPICE
model but they separate as much as possible the simulation algorithm from the device model.
For example, the Spectre simulator provides a Spectre Compiled Model Interface (CMI) for
Spectre developers and others to use C code directly for device modelling.
2.3.2 Verilog
The Verilog Hardware Description Language (Verilog HDL) was designed in 1984 to meet
the design demands of VLSI engineers working in the higher abstractive level to increase
the number of transistors in simulating digital circuits. Subsequently adopted by Cadence
Design Systems and Open Verilog International, VHDL has become an IEEE standard in
1995, i.e. IEEE Std 1364-1995 [? ].
Since the original Verilog language did not support analogue systems, the extensive use
of HDL languages led to a growing demand for high-level behavioural model for systems
and components for use in analogue and mixed signal system design. Thus, Verilog-AMS
standard was then developed by Accellera to include Verilog-A, a previously standalone
behavioural language used for analogue modelling in Spectre, and extending both the digital
part of the IEEE Std 1364 and the analogue part of Verilog-A [? ].
In the early days of Verilog-A and Verilog-AMS, the behaviour model was limited in
terms of accuracy for analogue devices. The language was first developed for design of
systems and thus the behavioural language was at that time not intended for complex physical
equations at the device level. Fig. 2.10 illustrates the mixed signal simulation environment
in early days. In addition, device modelling often led to long execution times compared
with SPICE models. Even so, the capability of behavioural modelling started to attract the
attention of device modellers struggling with low level implementation.
In 2002, the open-source tool supporting automatic conversion [? ] of Verilog-AMS
models to C codes was introduced. Since then, several proposals have been made to use
Verilog-AMS to efficiently develop compact device models [? ? ] to integrate with SPICE
like simulators. The report in 2010 [? ] showed comparable performance of their Verilog-
AMS device model against SPICE. The language has now become a major tool for device
2.3 Computer Interpretation of Device Model 23
Fig. 2.10 Verilog-A behaviour model in early mixed signal simulation environment
Fig. 2.11 Verilog-A(MS) extension for compact modelling with SPICE like simulator inte-
gration
24 TFT Compact Modelling
Table 2.3 Comparison between different model languages
SPICE Spectre CMI Verilog-AMS
Language C/Fortran C Verilog
Language level Low Low High
Easy to use No No Yes
Efficiency & Speed High High Low
Complexity High High Low
Simulator information
needed for developers
Simulation
algorithm &
limitations
Simulator
limitation on
equations
None
Users SPICE developers
CAD engineers,
Cadence
programmers
End users
model developers. Fig. 2.11 illustrates the relation between different Verilog languages and
the simulation flow in two types of simulators.
2.3.3 Short Summary of Comparison
Table 2.3 summarizes the comparison of different model languages. The SPICE model
development based on a low level language is only used by model developers of components,
which are not likely to change (due to heavy usage or technology maturity) in view of
resource requirements. In the meantime, the Verilog approach is ideally suited to meet the
modelling demands of ever-changing TFT or other device structures without requiring a
mature physical understanding of the devices or underlying material system. The direct
implementation of physical equations in Verilog-AMS will dramatically reduce the time
between development of new devices and subsequent circuit simulation.
Despite all the benefits of Verilog-AMS, the model is still slower and less efficient than a
well-developed SPICE model, due to the fact that the Verilog-AMS model should be converted
to a lower level language form. The converted form although automatically optimized by
the synthesizer (e.g. ADMS [? ]) cannot be as efficient as a SPICE model because the
latter is optimized directly in a lower level language. Therefore, it is recommended to use
SPICE for circuit simulation whenever it could offer sufficient accuracy. On the other hand,
Verilog-AMS is suited for devices that are new or under-development.
2.4 CAMCAS Model in Simulation Environment 25
Fig. 2.12 Circuit design and simulation flow using CAMCAS model in Cadence Design
Environment
2.4 CAMCAS Model in Simulation Environment
As discussed before, we implement the Cambridge’s TFT compact model (i.e. CAMCAS
model) directly into Verilog-A language for use in a Cadence Design Environment so as to
focus on developing a more accurate model for circuit simulations. The simulation flow in
the Cadence Design Environment is shown as Fig. 2.12.
The user extracts processing parameters based on the measurement results of their own
devices and incorporates them into the CAMCAS Verilog-AMS model. In addition, the
user can change the form of equations for better fitting to measurement results. Thus circuit
designers can use the usual route of circuit design by simulating their TFT circuits before
fabrication analogous to using the SPICE model in Cadence Spectre.
Fig. 2.13 shows an example of an IGZO TFT circuit simulated using the CAMCAS model
in Cadence Spectre. The simulation results show a voltage gain of 12dB in both transient
and AC simulation as shown in Fig. 2.14a and 2.14b, respectively.
2.5 Summary and Discussion
Physically-based compact models play an important role in computer-aided circuit design
and simulation. This chapter reviews the major contributions in TFT analytical modelling
and compares the pros and cons of SPICE and Verilog-AMS from the standpoint of device
26 TFT Compact Modelling
Fig. 2.13 A voltage amplifier used in simulation with CAMCAS model
model development. Brief guidelines are provided to decide on choice of modelling language
for implementation of models and to understand how models work within the simulator.
Regarding the device models, oxide TFTs are considered and two different approaches
are reviewed. While considering physical and material properties of oxide semiconductors,
both above- and subthreshold models have been presented. In particular, the above-threshold
model uniquely addresses carrier transport properties in oxide TFTs, such as percolation
conduction along with trap-limited conduction. Thus it is a fully-physical model. Also,
using a harmonic average technique, diffusion and drift current components have been
seamlessly combined to describe subthreshold current behaviour, providing good agreement
with measurements. Using a different, more empirical-based approach, a unified model is
discussed that covers both sub- and above-threshold regions with a single expression. This
model provides higher speed circuit simulation since it has only a few number of parameters.
The results presented here are essential for oxide circuit design and simulation, providing
designers with a preference for fully physical but slower simulations on the one hand, and
higher speed but less model complexity on the other.
The CAMCAS model described above is implemented in Verilog-AMS, and the validity
of the approach is demonstrated by way of a voltage amplifier circuit simulation.
2.5 Summary and Discussion 27
(a) Transient analysis for small signal amplitude at input and output
(b) AC analysis for gain and phase
Fig. 2.14 Simulation results of the voltage amplifier

Chapter 3
Small Signal Modelling
3.1 General Small Models
Small-signal model is used for linear approximation of many none linear electronic devices
including diodes, MOSFET and BJT, etc. when the signal under processing is reasonably
small compared with the DC bias of devices. The use of small-signal model significantly
simplifies the design procedure of many analogue circuits, especially amplifiers. Different
small-signal models exist for different electronic devices, for example MOSFET and BJT are
having different small-signal models due to their different structure and working principles.
However, researchers in the area of TFT circuit design are using the same small-signal model
as MOSFET. In spite of the similarity of their structures, TFTs are having a much bigger
contact resistance between different materials, more significant parasitic capacitance and
a severe instability problem. Therefore, it is helpful to reevaluate the small-signal model
specifically for TFTs.
3.1.1 Midband Small Signal Model
First, we review how a midband small signal model was developed. As linear systems are to
be designed out of none linear devices, the straightforward solution is to use a small part of
the none linear behaviour (I-V curves) to approximate a linear response (small signal model).
Therefore, under the assumption that the signal is sufficiently small, the linear approximation
would be equal to the derivative of the none linear device at the bias point. For a general 3
terminal device with terminal G, S and D (terminal names can be arbitrarily chosen, here
30 Small Signal Modelling
they are chosen in consistency with TFTs), The I-V formula can be written as:{
ID = f1(VGS,VDS)
IG = f2(VGS,VDS)
(3.1)
Here, VGS and VDS are the voltage drops between G-S terminals and D-S terminals, respec-
tively. As VGD can be calculated from VGS−VDS and IS =−ID− IG, Eq. (3.1) is enough to
represent the I-V of an arbitrary 3 terminal device.
For small changes of VGS and VDS, the current differences would approximately follow
the derivative of the ID and IG functions in Eq. (3.1).
dID =
∂ f1
∂VGS
dVGS+
∂ f1
∂VDS
dVDS
dIG =
∂ f2
∂VGS
dVGS+
∂ f2
∂VDS
dVDS
(3.2)
For sufficiently small signals and sufficiently good linearities at the bias point, the partial
derivatives can be treated as a constant. The small signal relations should follow:
id = gm1vgs+
vds
ro1
ig =
vgs
ro2
+gm2vds
(3.3)
where i and v in small cases represent the small change in current and voltage of the
corresponding terminals, respectively. The coefficient of vds for id or vgs for ig can be
represented as passive components (a resistor connection), while the coefficient of vgs for
id or vds for ig can only be represented by active components, a voltage controlled current
source (VCCS). Therefore, resistance is used to represent passive components (i.e. ro1 and
ro2) and transconductance is used to represent active components (i.e. gm1 and gm2).
Now, from Eq. (3.3) we have the linear approximation of the device at a fixed bias point
of VGS and VDS (Note that the coefficients in Eq. (3.3) can be a function of VGS and VDS, but
not a function of vgs and vds under the small signal assumption.) The corresponding small
signal model of the equation can be drawn as Fig. 3.1. This is a general form of a hybrid-pi
model which is consistent with both BJT and MOSFET. In the case of most transistors, VDS
does not affect IG. Thus, gm2 = 0. And for the case of MOSFET, the gate resistance is
huge and normally treated as open-circuit. Therefore, the corresponding components can be
removed.
The analysis reviewed above is a general approach for all three terminal devices. Thus it
should also be valid for TFTs at midband frequencies. However, as the parameters are derived
3.1 General Small Models 31
Fig. 3.1 Small signal model for a general 3 terminal device
from the derivative of I-V curves, a more physical representation of those parameters can be
complicated and some of the parameters should be represented as separate components.
3.1.2 High-Frequency Small Signal Model
An accurate calculation of the circuit response at midband frequency is not enough for
circuit designers as the bandwidth and phase margin should also be predicted when designing
circuits. This is especially crucial for amplifiers and active filters to prevent self-oscillation.
While midband small signal models can be developed through a general way from I-V curves,
the high-frequency small signal model can only be developed by considering I-V, C-V and
physical meanings of different components. This is why the high-frequency small signal
models are very different for CMOS and BJT despite the similarities on their midband
models.
The comparison of CMOS and BJT models is shown in Fig. 3.2 [? ]. The CMOS high
frequency model (Fig. 3.2a) is more consistent with the midband model that the parasitic
capacitors are added to the midband model while keeping the original connections. In
comparison, the BJT model (Fig. 3.2b) is less so as node B′ is added between rx and rπ
(which are the same resistance in the midband model). The separation of rx is due to
the physical representation of a base spreading resistance which is the resistance of the
connection to the base inside the device. The contribution of this resistor becomes more
significant at high frequency because of the reduced impedance of the parasitic capacitors,
namely Cµ and Cπ .
32 Small Signal Modelling
(a) CMOS model
(b) BJT model
Fig. 3.2 High frequency small signal models for CMOS and BJT
The review of CMOS and BJT high-frequency small signal models suggests that physical
structure should be considered while developing high-frequency models as the connections of
parasitic capacitances may vary and affect the overall performance of the model. Therefore,
it is imperative to evaluate the TFT structure to include physical resistance, capacitance and
their connections correctly.
3.2 TFT Small Signal Model
As discussed in the introduction section, an accurate TFT small signal model needs to
consider the physical representations and modelling not only for the sake of a simpler
3.2 TFT Small Signal Model 33
expression of each component in the midband model but also for an accurate modelling in
the high-frequency model. In this section, we will discuss the concerns at the stage of model
developing and report the developed models.
3.2.1 Midband TFT Model
As discussed in section 3.1, the midband model can be developed using the general approach.
Therefore, the small signal behaviour can be represented by a VCCS and an output resistor
in parallel. The major concern of this approach is the expression of the two components, gm
and ro. As the two components come from the derivative of IDS−VGS and IDS−VDS curves,
the static characteristic of TFTs should be considered first before deriving the expressions of
gm and ro.
The major concern here comes from the big contact resistance (RC) [? ? ? ? ? ?
] and the threshold voltage shift (VT shift) [? ? ? ? ? ? ] in TFTs which include
TFTs from different material families such as amorphous silicon, organic and metal oxide
semiconductors. Although TFTs are having a similar working principle with MOSFET,
the contact resistance (RC) is so dominant that even the static model should consider RC
as independent components. Most of the static models are developed based on a structure
shown in Fig. 3.3 where the I-V characteristics are modelled for the internal transistor and
the RCs (RS and RD here) are accounted for separately.
In this section, we will consider the effect of contact resistance and VT shift in the
midband TFT model.
The effect of contact resistance
As the overall I-V expression is complicated when considering RS, RD and the ideal TFT as
a whole, it is more convenient to derive the small signal model of the ideal TFT and then
consider the circuit as a linear network. Therefore, by using the I-V expression we can easily
derive a small signal model shown in Fig. 3.4a. As reviewed in Chapter 2, the general I-V
expression for a TFT can be written as:
IDS =
1
αp+2
K
W
L′
(VGS′−VT )αp+2 (3.4)
where K = (αp + 2)µ∗0 (
NC
NC+NtckTt
)C
αp+1
ox
Q
αp
re f
βsat . The transconductance gmi in in Fig. 3.4a can
then be calculated directly as:
gmi = K
W
L′
(VGS′−VT )αp+1 (3.5)
34 Small Signal Modelling
Fig. 3.3 The inner structure based on which static TFT models are developed
The roi in the figure, however, is harder to express in physical parameters. As the slope
of the output characteristics are normally modeled using an empirical Early voltage (VA)1, roi
is then calculated using:
roi =
VA
IDS
(3.6)
With the above equations, we can easily get an accurate midband small signal model for
the TFT of concern and design suitable gmi and roi by choosing W/L ratio, given that the
TFT technology and processing parameters are already modeled with known RS, RD and VA.
However, it is not so convenient in terms of measurements as the results will be overall I-V
curves directly. As the derivatives of the overall I-V curves can capture the overall gm and ro
1TFTs do not have the same short channel effect as CMOS does. But the output characteristics have similar
trend of having an Early voltage. Thus, it is usually modeled by an empirical Early voltage.
3.2 TFT Small Signal Model 35
(a) RC as separate component
(b) Overall midband model
Fig. 3.4 Midband small signal models
in a equivalent midband model shown in Fig. 3.4b (the general approach). It is worth finding
the relations between the two models shown in Fig. 3.4.
As the circuits are only consists of linear components, in this case only VCCS and
resistors, the circuit in Fig. 3.4a should be equivalent to the one in Fig. 3.4b according to
36 Small Signal Modelling
Thévenin’s theorem [? ? ]. From Fig. 3.4a, we have:
id =
vs′s
RS
id = gmi(vgs− vs′s)+
vds− idRD− vs′s
roi
(3.7)
Substituting vs′s and considering 2 RS = RD = RC, we get:
id = (
gmiroi
gmiroiRC +2RC + roi
)vgs+(
1
gmiroiRC +2RC + roi
)vds (3.8)
Compared with Fig. 3.4b where we have:
id = gmvgs+
vds
ro
(3.9)
As both models should capture the same derivatives of the overall I-V curves (i.e. gm and ro),
the relations should follow: gm =
gmiroi
gmiroiRC +2RC + roi
ro = gmiroiRC +2RC + roi
(3.10)
Here, we can derive the overall gm and ro out of the theoretical prediction of our transistor
models. While designing real circuit applications, this will be the equations to use to estimate
the circuit behavior. By solving Eq. (3.10), we can also get the values of internal components
from measurement results: gmi =
gmro
ro−gmroRC−2RC
roi = ro−gmroRC−2RC
(3.11)
This equation is very useful when the values of internal components are to be extracted out
of measurement results. It also provides a convenient way of checking the validity of the
model, which will be discussed later.
Eq. (3.10) and Eq. (3.11) not only show the relation between the static model param-
eters and the overall parameters from measurements but also reveal some insights of the
parameters:
2As the semiconductor layer and source/drain contacts are made of the same material and have identi-
cal geometries and similar properties, the contact resistances are considered to be equal at both sides for
convenience.
3.2 TFT Small Signal Model 37
1. The intrinsic gain gmro of both the overall performance and the ideal internal TFT are
the same. As the overall gm is reduced due to the contact resistance (in comparison
with gmi), the ro increases at the same rate making gmro = gmiroi. This also means that
the contact properties of the semiconductor layer and the electrodes do not affect the
intrinsic gain of the overall transistor. The measurement of gmro directly shows the
maximum achievable single-stage gain of the semiconductor technology.
2. The term gmiRC can be used to evaluate how different the measurement results will be
from the ideal TFT in the model. As gmiroiRC cannot be dominant over roi, otherwise
the overall gm ≈ 1RC (which is impractical as there’s no dependence on bias), and
RC << roi, the value of gmiRC should be around 0 1 (might be a bit higher than 1 but
should be around the order of magnitude).
The effect of VT shift
Another property that might affect the midband model is the VT shift under bias condition. As
the implementation of TFTs in AMOLED display proves that bias-induced VT shift must be
compensated especially when the analogue properties are to be used (i.e. the output current
needs to be actually controlled), the TFT small signal model should capture the behaviour to
help design and evaluate TFT analogue circuits.
The major concern of VT shift is that it would change the bias condition in effect, as in
the static models, the VT terms always appear in VGS−VT . Therefore, considering VT shift,
the expression of Eq. (3.5) can be rewritten as:
gmi = K
W
L′
(VGS′−VT −∆VT )αp+1
= K
W
L′
(VGS′−VT )αp+1
(
1− ∆VT
VGS′−VT
)
= K
W
L′
(VGS′−VT )αp+1−K
W
L′
(αp+1)(VGS′−VT )αp∆VT +O
(
∆VT
VGS′−VT
) (3.12)
Typically, ∆VT << VGS′ −VT , as the experiments show that the VT shift does not turn the
transistor off (i.e. ∆VT ∼ VGS′ −VT ) at least not within a reasonable time period. Hence,
the higher order terms can be omitted in the above Taylor expansion. The first order
approximation of gmi can then be written as follows:
gmi ≈ gmi0−K′∆VT (3.13)
38 Small Signal Modelling
Fig. 3.5 Midband TFT model considering VT shift
where gmi0 = K WL′ (VGS′ −VT )αp+1 is the initial value where there’s no VT shift, and K′ =
K WL′ (αp+1)(VGS′−VT )αp is the coefficient of the gmi change per ∆VT change. Here, as αp
is a constant value close to zero, K’ can normally be treated as a constant coefficient.
This means that the VT shift effect can be represented by a separate component. The
corresponding modification of small-signal model is shown in Fig. 3.5.
3.2.2 High-Frequency TFT Model
Device structure and physical meanings of all components need to be considered in high-
frequency small signal model, especially when capacitances come into the picture, as dis-
cussed in section 3.1 of the BJT model. The connection of contact resistances in TFTs
plays a similar role as the base spread resistance of BJT which is connected in series with a
parasitic capacitance. Here, as illustrated in Fig. 3.6 the contact resistance at source side (RS)
separates the overlap capacitance (COV S) and channel capacitance(Cch). Hence, RS might
not be negligible nor included in overall components (i.e. gm and ro) especially at high
frequencies. Combining the analysis of the midband model, the high-frequency small signal
model for TFT can be drawn as Fig. 3.7a. In comparison, the CMOS model adapted to
TFT parameters are shown in Fig. 3.7b. Here, COV S and Cch are considered to be the same
capacitor between source and gate terminals and the contact resistances are included in the
overall gm and ro.
3.2 TFT Small Signal Model 39
Fig. 3.6 Bottom-gate TFT structure considering passive components of the small signal
equivalent circuit. COV S and COV D are the overlap capacitance at source and drain side; Cch
is the channel capacitance; RS and RD are the contact resistances at source and drain side.
(a) TFT model
(b) CMOS model adapted to TFTs
Fig. 3.7 High frequency small signal models
40 Small Signal Modelling
In order to evaluate the difference between the developed model and the CMOS model,
we compare the expressions of the short circuit current gain (Ai) and the cutoff frequency of
the two different circuits.
For CMOS model, Ai can be calculated as:
Ai =
sCOV D−gm
s(COV D+COV S+Cch)
(3.14)
which contains one pole (at 0) and one zero (at gm/COV D). Assuming the zero is far from the
point of cutoff frequency. The unit-gain cutoff frequency can be calculated as:
fT =
gm
2π(COV D+COV S+Cch)
=
gm
2πCtot
(3.15)
where Ctot is the sum of all capacitances of the TFT.
In contrast, the current gain calculated for the TFT small signal model seen in Fig. 3.7a is
Ai =
−gmiroi+((2RC + roi+gmiRCroi)COV D+CchRC)s+COV DCchRC(RC + roi)s2
s(gmiCOV RCroi+(2RC + roi)(COV +Cch)+COV (RC + roi)RCCchs)
(3.16)
where COV =COV S+COV D is the total overlap capacitance. The equation shows two zeros
and two poles for this model. Assuming the poles and zeros are far from the cutoff point (for
linear assumption at the point in Bode plot), the cutoff frequency expression is derived as:
fT =
gmiroi
2π (gmiCOV RCroi+(2RC + roi)(COV +Cch))
=
gm
2π(Ctot −gmRCCch) (3.17)
The simplification of the above equation shows that the major difference between
Figs. 3.7a and 3.7b comes from the term gmRCCch. As gm is a term already contains
the RC, it is preferable to consider this term as a function of independent variables. Thus, by
substituting the gm term, the expression of gmRC is:
gmRC =
gmiroiRC
gmiroiRC +2RC + roi
(3.18)
As gmi, roi and RC are independent values depending on semiconductor and interface proper-
ties with positive values, the whole term should be smaller than one. This indicates that the
fraction Cch is of the total capacitance plays an important role in determining whether the two
models become identical. In the case when COV is dominant over Cch or when the value of
RC is very small or close to zero, the gmRCCch term can then be omitted and thus Eq. (3.17)
becomes the same as Eq. (3.15). The CMOS model can be used despite the connection of
RCs as in these cases the two high frequency models are equivalent.
3.3 Model Validation 41
In the case when the value of Cch is at least of the same order of magnitude as COV
or higher, the gmRCCch term can reduce around 50% of the total capacitance (for the case
when gmiRC ≈ 1) making the two models very different in terms of modelling of the cutoff
frequency. This also indicates that the CMOS model can be inaccurate especially when the
contact resistance and overlap capacitance are big and small, respectively. As the contact
resistance is known to be big in TFTs (from a few kΩ to several 100kΩ) and the reduction of
overlap capacitance is preferable at the processing side for the sake of making faster TFTs,
the inaccuracy of CMOS model might exist in most TFTs and may become more significant
as processing technique becoming mature (e.g. for self-aligned TFTs the overlap capacitance
is close to zero).
The other point to notice is that the assumptions used to derive Eq. (3.17) is supported by
calculating the actual values of zeros and poles of the transfer function. As the extra zeros
and poles are at way higher frequency compared with the cutoff frequency, they are not of
concern as the transistor is dominated by capacitor effects and is not working properly at the
frequency range.
3.3 Model Validation
From the theoretical analysis of small signal modelling, we know that the TFT small signal
model can be very different from CMOS model when the contact resistance and overlap
capacitance are big and small, respectively. In this section, we will evaluate the amount of
difference by measurement of IGZO TFTs’ cutoff frequency and the dominating s-parameters.
3.3.1 Measurement Setup
In order to evaluate the small signal model, we need to measure the current gain of the TFT
and compare the cutoff frequency to see the model difference quantitatively. The common
way of measuring the cutoff frequency of a transistor is to use a network analyser to measure
the s-parameters and convert them to h-parameters. The calculated h21 directly reflect the
short-circuit current gain of the device. Here, we use Keysight E5061B network analyser
(ENA) calibrated by CS-11 calibration substrate provided by GGB Industries, Inc. The
standard measurement setup is shown in Fig. 3.8. The bias-T provides DC bias to the TFT
under test and separates the small signal input and output from the DC circuitry. The TFT is
then connected to the ENA ports for s-parameter measurement.
The main reason of choosing the analyser is that it can provide low-frequency measure-
ment down to 5Hz. In contrast, most of the network analysers on the market are targeted
42 Small Signal Modelling
Fig. 3.8 Measurement setup for fT and s-parameters
above 100kHz range, which is already a range close to TFT’s cutoff. In the next section, we
will see that even with the network analyzer low-frequency measurement is still hard, as the
TFTs are more resistive at low frequencies.
The ENA in use can only provide DC bias at port 1. Therefore, the bias-T at port 1 is
already included inside the ENA. We still need to find a bias-T for port 2. As low frequency
is important for our measurement, we choose Picosecond 5546 bias-T for this purpose. The
low 3dB frequency is 3.5kHz, the lowest we managed to find on the market. We choose
CS-11 calibration substrate and model 10 high-frequency probe (from DC to 6GHz) from
GGB Industries, Inc. for the purpose of calibration, as the parasitics on the wires and the
probes, etc. should be calibrated out before s-parameter measurement.
The DC bias conditions are chosen to be VGS = 8V VDS = 15V to make sure the TFT
is working in the saturation region. It is to be noted that from the output characteristic
(Fig. 3.9) the TFT saturates later than VGS−VT , which is the saturating point for CMOS.
This is explained as the voltage drop on the contact resistance effectively reduced the VD′S′
on the internal TFT (Fig. 3.3). The device under test has following physical and geometrical
parameters: ts = 50nm, VT = 1.6V , Cox = 30nF/cm2, µ∗0 = 8.6cm
2/V · s. The device with
W/L ratio of 100µm/10µm is used for model validation and 50µm/10µm is used for stress
measurement.
3.3.2 s-parameters and fT Measurement
As fT is calculated through s-parameter measurements, it is essential to understand how it is
calculated and evaluate the measurement procedure as TFTs might have specific properties
which may make the measurement very different from standard CMOS.
The most significant difference for TFTs is that the devices are very resistive. As TFTs
are normally biased with a few volts to 20V level and the output current is normally around
a few or a few tens µA, the corresponding resistances are around 100kΩ or even a few
MΩ level. Resistance at this level is huge particularly in s-parameter measurement as s-
parameters are usually normalised with a characteristic resistance of 50Ω or 75Ω. For single
port measurement such as S11 and S22, the relation between corresponding impedance(ZL)
3.3 Model Validation 43
(a) Transfer characteristic
(b) Output characteristic
Fig. 3.9 I-V characteristic of the TFT under test
44 Small Signal Modelling
and Sxx(S11/S22) is:
Sxx =
ZL−Z0
ZL+Z0
(3.19)
where Z0 = 50Ω is the characteristic resistance. Here, as ZL is much larger than Z0, the
S11orS22 values should be very close to 1 (or very close to 0dB). This fact only changes at
higher frequencies when the impedance of the capacitors drops significantly. As discussed be-
fore, the frequency range of concern is the range below the cutoff frequency. The impedance
of the capacitor at the frequency range should be comparable with the internal components,
otherwise, the circuit performance will be dominated by the capacitors. Therefore, the
assumption will be valid in the whole frequency range of concern.
S11 and S22 are also called reflection coefficient. It expresses the ratio of the reflected
power to the incident power of an electromagnetic wave. As the reflection coefficient is close
to 1, the transmission coefficients (S12 and S21) should be small as most of the power are
reflected rather than transmitted. The experiment shows these two parameters are very close
to 0.
Now as we know the estimated value of the 4 parameters, we need to evaluate the equation
of h21 (Eq. (3.20)).
h21 =− 2S21
(1−S11)(1+S22)+S12S21 (3.20)
Here, the major complexity comes from the denominator. Therefore, the next question
is whether the denominator is dominated by some part of the terms or not. It is pretty
hard to tell which part of the denominator is more dominant intuitively, as both terms
of (1− S11)(1+ S22) and S12S21 are close to 0. One could estimate from the assumption
that 1− S11 has a similar order of magnitude compared with S12 or S21 to conclude that
(1−S11)(1+S22) term dominates over S12S21. A further check from experiment based on
the IGZO TFTs shows that the former term is 4 orders bigger than the latter term as shown in
Fig. 3.10. Therefore, the S12S21 term can be omitted when calculating the current gain.
Further, as S22 is very close to 1, the product of 1−S11 and 1+S22 is much more sensitive
to the change of S11 than S22. The final approximation of the equation is then as follows:
Ai = |h21| ≈ | S21S11−1 | (3.21)
Note that the approximation above is very accurate as the dominance of parameters is so
significant. A comparison based on experiment result is shown in Fig. 3.11. The estimation
gives 0.04% error in calculating the current gain of TFT within the frequency of concern.
Therefore, Eq. (3.21) can be used in the measurement of current-gain or fT of TFTs without
the measurements of S12 and S22.
3.3 Model Validation 45
Fig. 3.10 Comparison between terms of (1−S11)(1+S22) and S12S21
Now from the derivation and verification above, we know the dominating parameters
for TFT fT measurement are S11 and S21. Thus, to evaluate the difference of TFT model
and CMOS model, we need to evaluate and analyse the two parameters in both models. As
both the two measurements need to connect a matched load at port 2 of the network, the
equivalent circuit for the measurements is identical as shown in Fig. 3.12. The modelling of
each parameter based on the equivalent circuit will be discussed in the following subsections.
And the simulation will be based on the static and dynamic parameters extracted in Chapter 2.
S11 measurement and analysis
Fig. 3.10 and Fig. 3.11 shows that the measurement at lower frequencies is very noisy
especially when S11 is involved. The main reason is the contribution of the 1− S11 term.
As discussed before, the S11 parameter is very close to 1 due to the near open-circuit
characteristic of capacitors at low frequencies. Therefore, the value of 1−S11 highly depends
on the measurement accuracy of S11. According to the datasheet of the network analyser
E5061B, the measurement accuracy for S11 with different calibration kit is around 0.03 and 2
degree for magnitude and phase measurement respectively, when average factor equals to 1
and 10Hz bandwidth is selected. However, in order to measure the parameters for the device
46 Small Signal Modelling
(a) Calculated h21
(b) Normalized error
Fig. 3.11 Comparison between Eq. (3.20) and its approximation Eq. (3.21)
3.3 Model Validation 47
Fig. 3.12 Equivalent circuit for S11 and S21 measurement
under test (DUT), the accuracy is not enough as the values of the S11 magnitude and phase
are 1 order smaller than the corresponding accuracies.
Further, after checking the measurement results, we noticed that the major uncertainty
comes from the shift of the machine property over time. As this shift in rather slow compared
with one cycle of a frequency sweep, we choose to do two quick sweeps with and without
the device connected to measure the S11 value. The open-circuit values are then subtracted
from the measurement results to cancel the property shift of the machine.
The measurement and simulation results are shown in Fig. 3.13. As can be seen, TFT
model fits much better compared with adapted CMOS model. The major difference comes
from the magnitude measurement as the measured curve drops, which suggests that there’s at
least an extra pole for the S11 expression of TFT model higher but close to the frequency of
concern. The calculation based on CMOS model gives the S11 model below:
S11CMOS ≈−
−g20+(COV S+Cch)g0s+COV D(COV S+Cch)s2
g20+(2g0COV D+g0(COV S+Cch))s+COV D(COV S+Cch)s
2 (3.22)
where gx = 1rx is the conductance of the corresponding resistor. The conductance terms
are used to make the equation looks simpler. An approximation is also used to simplify
the equation based on the assumption that g0 >> gm and g0 >> go. This is particularly
true in the case of TFT because of the high resistance of TFT devices. For example, 1/gm
is normally around a few kΩ to a few 100kΩ and ro is around a few MΩ. However, the
characteristic resistance is 50Ω. Therefore the conductance of the characteristic resistance
g0 should be more dominant compared with all other resistances and conductances in the
48 Small Signal Modelling
(a) Magnitude
(b) Phase
Fig. 3.13 Magnitude and phase measurement and simulation for S11 parameter based on TFT
model and adapted CMOS model
3.3 Model Validation 49
small signal model of TFT (or the adapted CMOS one). The assumption is also used in the
derivation of S11 of TFT model. This model suggests that the equation has 2 zeros and 2 poles.
Calculation based on Eq. (3.22) shows that the 2 zeros are at 3.4462GHz and 10.853GHz and
2 poles at 2.4898GHz and 15.022GHz. As the zeros and poles are all far above the frequency
of concern (i.e. below 10MHz), the S11 modelled by the CMOS model would remain at 1 at
the frequency range as suggested in Fig. 3.13a (which suggests a very close to open circuit
behaviour).
The calculation based on the equivalent circuit shown in Fig. 3.12 gives the S11 expression
as follows:
S11T FT =−
−gtotgcg20+a1s+a2s2+(gc+goi)CchCOV SCOV Ds3
gtotgcg20+b1s+b2s
2+(gc+goi)CchCOV SCOV Ds3
, (3.23)
where gtot = gmi+gc+2goi
a1 = [gcgtotCOV S+gc(gc+goi)Cch]g0− (gc+goi)g20Cch,
a2 = (gc+goi)CchCOV Sg0,
b1 = [gcgtotCOV S+2gtotgcCOV D+(gc+3goi)gcCch]g0+(gc+goi)Cchg20,
b2 = (gc+goi)g0Cch(COV S+2COV D).
Here, the equation has 3 zeros and 3 poles. To further evaluate the difference between
the two models we simulated their S11 parameters. The simulation results are shown in
Fig. 3.14. Just as the figure suggests, two zeros lie between two poles to make a valley of
the magnitude curves for both models. However, these poles and zeros are at much higher
frequencies compared the cutoff of the transistor. Therefore, the simulation results only show
a flat line below 10MHz for CMOS model. As for the TFT model, the numeric calculation
shows that there are 3 poles at 54.755MHz, 2.8314GHz and 19.389GHz. The zeros are at
54.947MHz, 4.5660GHz and 11.981GHz. The 2 zeros and 2 poles at GHz level have similar
values compared with the CMOS model to make a similar shape of the curve at very high
frequency. However, they would not create much difference at the low frequency range of our
concern either. The major difference we’ve noticed is the extra zero and pole at 54.947MHz
and 54.755MHz, respectively. These two points are pretty close to the cutoff frequency and
the frequency of concern. From further inspection of Fig. 3.13 and Fig. 3.14, we notice that
it is these pole and zero that cause a slight drop of the S11 magnitude. As the pole is slightly
smaller than the zero (although only by less than 1%), the magnitude starts to drop a little
before the effect is cancelled by the zero. This drop distinguishes the two model at around
10MHz range as the measurement in Fig. 3.13 suggests. This also suggests that the TFT
50 Small Signal Modelling
Fig. 3.14 S11 simulation of the TFT and CMOS models
model (with the contact resistance and the separation of the channel and overlap capacitance)
captures an extra pole and zero, which results in a better accuracy than the CMOS model.
It can be noted that |S11| equals to 0dB (or 1) at both very low frequencies and very high
frequencies. This can be explained by the connection of the COV S as it acts as open-circuit at
low frequencies (S11 = 1) and short-circuit (S11 =−1) at high frequencies.
Here, as the major accuracy improvement comes from the extra zero and pole, it is worth
finding the exact expression of their analytic form. The accurate expressions can be directly
extracted from the Eq. (3.23) by solving the cubic equations. However, the expressions
become too long for the purpose of estimating the positions of the extra zero and pole.
Alternatively, we discovered that by taking out the Cch in CMOS model, the simulation
results of the two models become very similar at high frequencies (shown in Fig. 3.14).
Therefore, we could compare the coefficients of Eq. (3.23) and Eq. (3.22) (taken out the Cch
term) to find the estimated expression of the extra zero and pole assuming that the CMOS
model contains all the poles and zeros except the extra ones.
Considering the matching of coefficients, we found the estimated expressions as:
3.3 Model Validation 51

fpe =− gtotgcg02π(g0+gc)(gc+goi)Cch
fze =− gtotgcg02π(g0−gc)(gc+goi)Cch
(3.24)
where fpe is the frequency of the extra pole and fze is the frequency of the extra zero. Here,
the expressions give a rather accurate estimation of the extra pole and zero of 54.763MHz and
54.946MHz, respectively, while the numeric calculation gives 54.755MHz and 54.947MHz.
Here, with the approximation of the extra zero and pole, one can easily draw the S11 curves
without simulating of the more complicated equivalent circuit. It also provides support for
the possibility of fitting a S11 measurement with one pole and one zero.
S21 measurement and analysis
As for S21, the simulation and measurement results are shown in Fig. 3.15. The results show
that the difference of S21 between models is less significant compared with S11. This is
because of the parameter varies much in a log scale axis (dB) and, therefore, the difference is
not visibly prominent in comparison with that of S11. For example, the measurement value
at 8MHz is |S21| = 2.85×10−3. The modelled value are |S21T FT | = 2.88×10−3 (yielding
1.1% error) and |S21COMS |= 2.69×10−3 (yielding 5.6% error).
The analytic expression of S21 in CMOS model is shown as Eq. (3.25):
S21CMOS =
2g0(sCOV D−gm)
g20+(2COV D+COV S+Cch)g0s+COV D(COV S+Cch)s
2 (3.25)
The equation shows that there are two poles and one zero in the model. Calculation based
on the equation shows that the zero is at 6.107MHz and the two poles are at 2.490GHz and
15.02GHz. Again, as the poles are all far above the frequency of concern, they would not
affect the measurement results below 10MHz. The results that there’s only one dominant
zero within the frequency range. The other point that should be noticed is that at very low
frequencies Eq. (3.25) yields to:
S21CMOS =−
2gm
g0
(3.26)
Here, the g0 = 1/50Ω−1 is a known value. Therefore, the S21 measurement can directly
reflect the small signal gm for the CMOS model. As discussed in section 3.2.1, the TFT
and CMOS models are equivalent at low frequencies as the capacitances can be ignored.
Therefore, this gm can also be used to extract the gmi for TFT model at lower frequencies.
52 Small Signal Modelling
(a) Magnitude
(b) Phase
Fig. 3.15 Magnitude and phase measurement and simulation for S21 parameter based on TFT
model and adapted CMOS model
3.3 Model Validation 53
As for TFT model, the equivalent circuit for the S21 calculation is the same as the one
used for S11 as the equivalent connection for the measurements are the same (Fig. 3.12).
Hence, we could derive the equation of S21 as below:
S21T FT = 2g0
−g2cgmi+(gcgtotCOV D+goigcCch)s+(gc+goi)COV DCchs2
gtotgcg20+ c1s+ c2s
2+(gc+go)CchCOV SCOV Ds3
, (3.27)
where,
c1 = (gc+goi)Cchg20,
c2 = (gc+goi)Cch(COV S+2COV D)g0.
Here, the equation shows two zeros and three poles for TFT model. Based on the parameters
of the device under test, we have that the zeros are at 5.501MHz and 60.90MHz and that
the poles are at 54.76MHz, 2.831GHz and 19.39GHz. Similar to the case for S11, there’s
one extra zero and one extra pole at 60.90MHz and 54.76MHz, respectively. These extra
zero and pole would also contribute a slight drop on the magnitude of S21 as they are very
close together, just as the case for S11. The difference here is that there’s a dominant zero
at 5.501MHz which is different to the 6.107MHz zero for the CMOS model. Hence, the
difference of the dominant zero contributes to the major difference between the CMOS and
TFT model. And the difference caused by the extra zero and pole becomes less prominent.
Here, the dominant zero for S21 can be expressed as:
fz0T FT =
gc
(√
(goiCch+gtotCOV D)2+4gmi(gc+goi)CchCOV D−goiCch+gtotCOV D
)
4πCchCOV D(gc+goi)
(3.28)
whereas the dominant zero for CMOS model can be express as:
fz0CMOS =
gm
2πCOV D
(3.29)
While CMOS model gives a simpler solution for the dominant zero for the S21 parameter, it
does not count the contribution of the channel capacitance (Cch). The TFT model, however,
accurately models the dominant zero with the contribution of Cch but yields a much more
complicated equation.
Again, at low frequencies Eq. (3.27) yields to:
S21T FT =
−2gcgmi
gtotg0
(3.30)
54 Small Signal Modelling
Fig. 3.16 S11 simulation of the TFT and CMOS models
Changing the conductance terms into resistance terms and combining Eq. (3.10), we have:
S21T FT =
−2gmiroi
(gmiroirc+2rc+ roi)g0
=−2gm
g0
(3.31)
This is exactly Eq. (3.26). This confirms that the CMOS and TFT model can be equivalent at
low frequencies.
fT measurement and analysis
As discussed, we can use Eq. (3.21) to calculate the short-circuit current gain of the TFT
with enough accuracy. Therefore, we used the measured S11 and S21 to derive the current
gain of the TFT under test and then use a linear fitting to get the value of the fT .
The measurement results of fT along with simulations based on the TFT and CMOS
model are shown in Fig. 3.16. The measurement results show a cutoff frequency of 3.11MHz
while the proposed TFT and CMOS models predict cutoff frequencies of 3.14MHz and
2.72MHz, respectively. This yields an error of 1% and 12.5%, respectively.
Here, we proved that the TFT model presented here is more accurate to predict the fT
compared with the CMOS counterpart. However, the measurement results of |h21| or |Ai| only
3.3 Model Validation 55
became consistent with the model at frequencies around MHz level. At lower frequencies,
the measurement became very noisy as illustrated in Fig. 3.11. However, as shown in the
analysis of Eq. (3.16), the |Ai| curve should be a straight line at lower frequencies as it is
dominated by a single pole at 0Hz. The main reason for the discrepancy is the measurement
accuracy of S11, especially at low frequencies. As the value of |S11| is very close to, if not
exactly equals to, 0dB at very low frequencies, the noise of the measurement becomes the
major contribution to its value. Therefore, as Eq. (3.21) suggested that the accuracy of |Ai|
depends on the subtraction of S11 and 1 (0dB), the noise of the measurement at this frequency
range would dominate the results of |Ai| and make them unreliable. This brings a concern for
the measurement of other TFTs with lower cutoff frequency, which means the frequency of
concern is lower, or with smaller size, which means that the capacitances are smaller making
the gate-source port behave even closer to open-circuit. Therefore, we should use a fitting
method to fit the S11 parameter before using its value to calculate |Ai| for the cases described
above. More detailed discussion regarding S11 fitting will be discussed in the next subsection
and also be used to measure the VT shift effect in fT measurement.
3.3.3 fT and VT shift
In this subsection, we will discuss the effect of the VT shift. As the accuracy of TFT model is
proved in the s-parameter and fT measurements, we would focus on the TFT model.
VT shift is another important factor for TFTs, as this is one the major concerns in TFT
based circuit designs, especially where TFTs’ analogue properties are of concern, for example
in RFID tags. For the case of the small signal model, the TFT is used as a voltage controlled
current source for the input of the small signal. Therefore, it is imperative to consider the
impact of VT shift on small signal model.
In order to examine its influence on the small signal behaviour, a constant bias stress
measurement is needed to measure both fT and VT of the transistor. However, simultaneous
measurement of the two parameters is not practical as the measurements of them need two
different connections, i.e. fT measurement needs network analyser and isolation for DC bias
and small signal input and output, however, the VT measurement needs I-V sweep to measure
the transfer characteristics (which we use KEITHLEY 4200 to measure). Therefore, we need
to find an alternative way to measure both parameters other than keep switching between
different measurement platform.
Here, we decided to use two different constant bias measurements and connect the two
parameters through gm as a bridge. The basic idea is that although fT and VT can not be
obtained simultaneously, the gm value can be obtained together in the measurements of both.
In specific, gm can be obtained through derivative of transfer characteristics as discussed in
56 Small Signal Modelling
section 3.1.1. It can also be obtained through low-frequency S21 measurement as discussed
in section 3.3.2. Also, as VT directly affects the value of gm (gmi is considered to be near
linearly related to the overdrive voltage (VGS−VT )) and gm also relates with fT , gm can be a
perfect link between the two measurements.
fT and gm
As discussed in section 3.3.2, a fitting method should be applied to the S11 data to obtain a
better low-frequency response for the current gain result. Here, as the device under test is
smaller in channel width and the cut-off frequency is lower, it is necessary to use the method
for better accuracy. The measurement result of S11 is shown in Fig. 3.17. The results are
fitted using 1 zero and 1 pole approximation following Eq. (3.32):
S11 ≈ 1+as1+bs (3.32)
where a and b are fitting parameters. The measurement results are fitted using MATLAB.
Here, as illustrated in Fig. 3.17, the measurement results are not reliable below 1MHz for
magnitude measurement and below 100kHz for phase measurement. The major cause of
the unreliable results is that the value of |S11| or its phase drops below the noise level at
low frequency range. Therefore, the fitting method is imperative to obtain a reasonable
low-frequency response. In addition, as the cut-off frequency for the device under test in this
subsection is around 1.5MHz, which is close to the unreliable range of |S11| (below 1MHz),
fitting method is even more important for a better accuracy, especially for capturing the small
change of fT caused by VT shift.
In order to capture the fT change under stress measurement, we kept the bias stress for 8
hours and measure the corresponding s-parameters. The converted |h21| with and without the
fitting of S11 are shown in Fig. 3.18. As illustrated, the |h21| values without fitting are rather
random at lower frequencies, which cannot reliably capture the change of the curves versus
stress time. However, with fitted S11, we can clearly capture the drop of the cut-off frequency
when the stress time increases, as illustrated in the inset of Fig. 3.18b.
The low-frequency measurement of S21 can be used to extract gm following a derivation
from Eq. (3.31):
gm =
g0|S21|
2
(3.33)
Here, we can use the flat part of the |S21| measurement and calculate the average of |S21| as
shown in Fig. 3.19. The value of |S21| drops when bias time increases, which is consistent
with the drop of gm caused by the VT shift.
3.3 Model Validation 57
(a) Magnitude
(b) Phase
Fig. 3.17 Magnitude and phase measurement and fitting for S11 parameter based on single
pole and zero approximation
58 Small Signal Modelling
(a) with S11 fitting
(b) without S11 fitting
Fig. 3.18 h21 results with and without S11 fitting
3.3 Model Validation 59
Fig. 3.19 S21 measurement showing low frequency range for gm extraction
By extracting gm through Fig. 3.19 and the corresponding fT through Fig. 3.18b, we can
get the fT vs. gm relation as shown in Fig. 3.20. The results show a linear approximation to
Eq. (3.17).
gm and VT
The gm vs. VT relation can be measured through I-V measurement of the device. The TFT
under test was biased at VGS = 8V and VDS = 15V and I-V sweep was done every logarithmic
time interval in order to extract the gm and VT . The constant stress bias is disrupted for a
short time due to the measurement. However, because the sweep time (VT measurement) is
much shorter compared with the bias time, we assume that the short pause for the constant
stress can be omitted. Notwithstanding this, the results showed that VT continued rising after
the sweep and the extracted value is then used to extract the relation between gm and ∆VT .
The extracted results are illustrated in Fig. 3.21.
Combining the results of Fig. 3.20 and Fig. 3.21, we can get the fT vs. ∆VT relation as
illustrated in Fig. 3.22. The corresponding VT was obtained through cubic polynomial fitting
of the curve in Fig. 3.21. The error bar here is the standard deviation of the fitting to obtain
the corresponding result. In specific, the standard deviation of ∆ fT was obtained from the
60 Small Signal Modelling
Fig. 3.20 fT vs. gm relation through S-parameter measurement
Fig. 3.21 gm vs. VT shift relation through stress measurement with I-V sweep
3.4 Summary and Discussion 61
Fig. 3.22 Extracted ∆ fT vs. VT shift relation. The error bar here is the standard deviation of
the fitting to obtain the corresponding result.
linear fitting to obtain the corresponding fT . The standard deviation of ∆VT was obtained
from the polynomial fitting of the curve in Fig. 3.21.
The ∆VT increased to +0.2V in total after the 10 hours bias stress and the respective ∆ fT
drops to 0.08MHz almost linearly. This is due to the relatively small ∆VT compared with VGS
which leads to a first-order approximation of Eq. (3.17). From Eq. (3.13) & (3.17), we have:
∆ fT ≈− roi(2RC + roi)(COV +Cch)2π (gmiCOV RCroi+(2RC + roi)(COV +Cch))K
′∆VT = β∆VT (3.34)
where β is the constant found to be about−3.2×106[Hz/V ] for the examined TFT. Eq. (3.34)
allows estimating the shift in unity gain frequency with threshold voltage shift. Here, the
coefficient β will be different for different material- and process-based TFTs.
3.4 Summary and Discussion
Small signal models are indispensable for the design of analogue circuits, especially in
the former for the correct phase margin and bandwidth of amplifiers and analogue filters.
This chapter reports on an accurate small signal model that takes into account the contact
62 Small Signal Modelling
Table 3.1 Summary of parameters for the CMOS and TFT models
Category RC ≈ 0 Cch <<COV General Case
CMOS and TFT
model equivalence
Equivalent Equivalent Not Equivalent
Parameter Relation
gm = gmi =
dIDS
dVGS
gm =
dIDS
dVGS
gmi =
gmro
ro−gmroRC−2RC
ro = roi =
dVDS
dIDS
ro =
dVDS
dIDS
roi = ro−gmroRC−2RC
Cut-off frequency fT =
gm
2πCtot
fT =
gm
2π(Ctot−gmRCCch)
VT shift terms gmi = gmi0−K′∆VT K′ ≈ gmi0VGS−VT 0
resistance, parasitic capacitance, and threshold voltage shift while introducing internal
transconductance (gmi) and output resistance (roi). The proposed TFT model yields a 1%
error in predicting the unity gain frequency, in contrast to 12.5% error using the CMOS
model. It also provides a better fit to the measured s-parameters.
More importantly, the theoretical analysis suggests that accuracy improvement stems
from Cch & RC connection in the TFT model. It also suggests that the CMOS model can
be inaccurate especially when the channel capacitance is more dominant and the contact
resistance (RC) is bigger. Further to the discussion, the summary of the key parameter
relations and equivalence of CMOS and TFT model are shown in Table 3.1.
The increase of RC due to downscaling of TFTs indicates that the proposed TFT model
can be more beneficial to use in smaller devices. As RC and its separation of channel
capacitance and overlap capacitance generally exist in many other types of device structures
and material families, the model is potentially applicable to other TFTs fabricated on insulator
substrates such as glass and plastic. Additional bulk parasitics should be considered when
modelling TFT on a semiconductor substrate.
Chapter 4
TFT analogue circuit building blocks
4.1 Status of TFT Circuits
Since the success of TFTs in TFT-LCD and AMOLED industry [? ? ], using TFTs to achieve
all kinds of functions that could otherwise only be realized by CMOS or BJTs has become
an appealing topic for researchers in the field [? ? ? ]. Despite the success in digital logic
and ADCs, analogue TFT circuits are still in its infancy. Although quite a few amplifiers
have been reported in recent years, few has reported the VT shift compensation and many are
very much relied on tuning the external power supply. However, in the CMOS counterpart,
bias independent and stable op-amps are used as modular in many analogue applications [? ].
Therefore, a more generally usable op-amp block is needed to design a more complicated
TFT circuit systems and to implement TFT circuits in a wide range of analogue applications.
4.2 Challenges of TFT Analogue Circuits
TFTs fabricated with different semiconductor materials are generally governed by different
internal physics. However, the problems we meet in designing circuit could be similar. Here,
we list several outstanding challenges of TFT circuit design.
1. More Resistive Devices
TFTs are generally more resistive compared with the conventional CMOS devices. This
is due to the lower mobility of the semiconductor compared with crystalline silicon.
As the electron or hole mobility (500-100 cm2/V · s for µe and 100-400 cm2/V · s for
µh) in Si is normally 2 orders higher than the semiconductors used in TFT devices
(around 1-20 cm2/V · s for both except polysilicon). In addition, the insulator layers of
TFTs are normally thicker than CMOS which leads to a smaller Cox.
64 TFT analogue circuit building blocks
Therefore, the current voltage level becomes very different compared with conventional
CMOS design. For example, at a similar voltage bias, TFTs will normally working
at a much lower current level. This means that other components in the circuit
(such as resistors, diodes etc) has to be working in a similar current and voltage
level (i.e. not several orders different). Therefore, the resistors in the circuit need
to have a much bigger resistance (approximately 2 orders larger than the ones used
in CMOS). However, metal track resistors would take excessive area to achieve big
enough resistance.
2. Lacking of complementary device
The other difficulty of designing TFT gain stages is lacking of complementary devices.
In specific, n-type organic TFTs are unstable or with very low equivalent carrier mobil-
ity. In the meantime, reliable p-type metal oxide TFTs does not exist either. However,
processing limitations restrains circuit designers to integrate different material fam-
ilies on the same substrate. Here, as mono type (n-type or p-type) circuit design is
symmetrical, we take IGZO TFTs as an example where only n-type TFTs are available.
N-type transistors are generally good to be used as a current sink, where the source
terminal should be grounded and current flows into the drain of the transistor. Here,
the circuit will benefit from the high small signal impedance of the output curve, as the
gate-source voltage (VGS) can be easily maintained through fixed voltage bias.
However, designing a current source (other than sink) with n-type transistors becomes
much harder as the current should flow out of the source of the transistor (to supply
current to the load). Therefore, the voltage level at the source terminal cannot be set
at a fixed bias making it difficult to maintain a fixed VGS and hard to benefit from
the high output resistance from output characteristics. As n-type gain stages need a
current source as load for amplification, the design of amplifier with high gain becomes
difficult.
3. VT shift
VT shift problem is one of the most recognised issues in TFT circuits. Successful
compensation of VT shift solves the stability issue in AMOLED display leading to a
great success in AMOLED panels. As discussed in chapter A, a switched capacitor
architecture is used for the compensation. However, switched capacitor circuits needs
extra clock based biasing circuitry to be functional. The major difficulty in design
is due to the stretched-exponential behaviour with respect to time, which can be
4.3 Building Blocks and Simulations 65
mathematically expressed as:
∆VT = (VGS−VT )
(
1− exp
(
−
( t
τ
)β))
(4.1)
The equation is highly initial condition dependent. With a few switching, the coeffi-
cient β and τ cannot be the same as the initial condition before the TFT was turned on,
making it difficult to predict the behaviour afterwards. The switched capacitor circuits
was therefore used to sample the VT . However, in analogue amplifier, we normally
expecting a continuous amplification. This effect can be cancelled as ∆VT is propor-
tionally related with VGS−VT for certain TFT connections [? ]. In short, when TFTs
are connected in series the voltage dividing behaviour will be VT shift independent.
When TFTs are connected as a current mirror, the current copying behaviour will be
VT shift independent. This discovery will be used in the circuit blocks we design in the
next section.
4.3 Building Blocks and Simulations
Several analogue building blocks for n-type TFTs are designed with the aim of realizing a full
op-amp in TFTs. It is worth mentioning that although TFT based amplifying stages has been
reported in many publications to exhibit some gain, biasing circuitries are mostly ignored.
However, a stable and supply-independent biasing circuitry is indispensible for a stable
performance in practice where the power supply could be less accurately controlled than the
power sources used in a labortory, for example a battery or a super-capacitor. In addition,
for wearable applications, it is more preferable to use fully TFT based flexible circuits and
remove the rigid CMOS based biasing circuitry. In this section, we will design several
analogue building blocks including voltage reference, current mirror, current reference and a
differential amplifying stage. Althought the designs here are aimed at realizing an op-amp,
the building blocks are applicable to other applications and designs.
4.3.1 Voltage Reference
Many applications need a stable voltage reference to supply an accurate voltage. For example,
a DC-DC converter would need a reference to maintain the output at an accurate level. An
ADC would need a reference to compare and convert the measured voltage to digital signal.
Here, we designed a supply independent voltage reference. Luis Toledo, et al. have reported
a circuit with 4 transistors to generate a VT related voltage reference where one transistor is
66 TFT analogue circuit building blocks
Fig. 4.1 Voltage reference circuit with all TFTs working in saturation region
working in linear region [? ]. Here, we designed the circuit with the same concept but made
all transistors working in saturation region. By changing all transistors to work in saturation,
the circuit benefits from a VT shift independent output [? ]. The proposed circuit is illustrated
in Fig. 4.1.
Here T1 and T2 are designed with the same W, W1 =W2. Based on the TFT saturation
model reported in section 2.2.1, the output voltage can be expressed as:
Vout =
1+2β1−β2
1+2β1
·VDD+ 3β2−2β1−11+2β1 ·VT (4.2)
where
β1 ≡ 2+α
√
W3
W2
, β2 ≡ 2+α
√
W5
W4
(4.3)
The VDD term can be cancelled if the following condition is met:
β2 = 2β1+1 (4.4)
Therefore,
Vout = 2VT (4.5)
4.3 Building Blocks and Simulations 67
To control the output voltage to be n ·VT is possible if one adds more TFTs in the TFT
ladder of the first stage. Here, 2VT is enough for our design. One interesting point here is that
Vout can decrease with an increased VDD if β2 > 2β1+1. This is very useful when a negative
feedback is needed from the power supply.
As the circuit requires all TFTs to work in saturation region, we could calculate its
working range. The lower limit of the working range is when VDD is just enough to turn on all
the TFTs at the TFT ladder. Thus, we have VDD > 3VT . The upper limit of the working range
is limited mainly the working condition of T5. As Vout remains a constant, high VDD would
eventually increase the gate voltage of T5 making it work in linear region. Therefore, by
writing down the saturation condition of T5, we can get the expression of the whole working
region:
3 ·VT <VDD < (5+4β1) ·VT (4.6)
Here, a bigger β1 could expand the working range by increasing the upper limit. For a more
general case where β2 > 2β1+1 (thus a inverse related Vout with respect to VDD), we have:
3 ·VT <VDD < 2+3β2−2β1β2−2β1 ·VT (4.7)
The simulation results for two different β1 are shown in Fig. 4.2. Here, W1/L1 =
50/20µm. The sizes of other transistors follow Eq. 4.4. The simulation results proves that
the higher limit can be controlled by the value of β1. Both circuits have an output voltage
of 2.45V with and error of 0.05V in a 5V range. Considering the voltage supply of most
applications would only vary less than 1V, the above design could be enough.
4.3.2 Current Mirror
As mentioned earlier, lacking of complementary devices is one of the challenges for TFT
circuit design. Specifically, the load of fully n-type amplifying stages (i.e. resistor load or
diode connected n-type load) often has lower small signal output resistance compared with
a p-type load. [discussed in Appendix A] Also, as p-type current mirror is not available,
differential pair could not benefit from the current steering as in the case of CMOS differential
gain stage. To design a circuit block with the same functionality is very beneficial in terms of
design flexibility as well as increasing the gain of amplifier stages.
Sanjiv and Nathan had reported a mirrorable current source in [? ]. Although the design
was mirrorable in the VDD side, it needs 2 extra bias voltage to set the current level which
do not copy current in the same way as a p-type mirror. Here, we redesigned the circuit and
achieved a pseudo p-type current mirror which could replicate the function of a real p-type
68 TFT analogue circuit building blocks
Fig. 4.2 Simulation results for the proposed voltage reference circuit with two different values
of β1
Fig. 4.3 Pseudo p-type current designed with all n-type TFTs
mirror which is shown in Fig. 4.3. The proposed circuit has an extra requirement of output
voltage (Vo), as all TFTs especially those in the feedback unit should work in saturation
region. The ground of feedback unit (T3-T6) are now connected to a reference voltage Vre f in
order to tune the allowable output voltage range which will be discussed soon. The design
4.3 Building Blocks and Simulations 69
here could replace the p-type mirror in many CMOS design and make many designs available
in fully n-type TFT design and keep the benefit of the complementary architecture.
To ensure the circuit’s functionality, all TFTs should work in saturation region. This is
mainly limited by T4 and T6 considering a changing in the level of Vo. Therefore, we have:
V1 >Vo−VT , and V2 >V1−VT (4.8)
By calculating the values of V1 and V2, we have the allowable output voltage range as:
Vi+
1
2
Vre f − 12(VDD+VT )<Vo <
1
2
(
Vi+Vre f +VT
)
(4.9)
Thus the range of the output voltage is:
Vrange =
1
2
(VDD−Vi)+VT (4.10)
To maximize the output voltage range, one should design a bigger VDD−Vi, which is the
overdrive voltage of T1 (meaning smaller W/L ratio is more beneficial for a bigger range of
Vo). In addition, as the term 1/2Vre f appears at both side of the upper and lower limit of Vo,
Vre f could be controlled to change position of the range but not affecting the width of the
range. The circuit is simulated with different Vre f values, which is shown in Fig. 4.4a. Here,
W1,2 is chosen to be 50µm. And T3-T6 are designed with the same size. As can be seen from
the figure, higher Vre f shifts the allowable range of Vo to a higher position but maintaining
the width of the range. Fig. 4.4b illustrates the simulation results with different W1,2. As
expected by the analysis above, shorter W1,2 widens the allowable range. The lower limit of
the allowable range is pushed further to a lower voltage level while the upper limit shifts only
a little lower. Therefore, designer could change Vre f and W1,2 to design the output voltage
range with a desired position and width.
4.3.3 Current Reference
With the pseudo p-type current mirror available, we could implement the current reference
circuit which is widely used in CMOS amplifier biasing. The proposed circuit is shown in
Fig. 4.5. The CMOS version of this circuit has been reported in [? ] where subthreshold
operation has been considered. Here, we consider the circuit to work in saturation region. As
the pseudo p-type mirror simply copies the current of T1 to T2. The reference current can be
derived by solving the equation below:
70 TFT analogue circuit building blocks
(a) Simulation results of the pseudo p-type current mirror with different Vre f values
(b) Simulation results of the pseudo p-type current mirror with different W1,2 values
Fig. 4.4 Simulation results of the proposed pseudo p-type current mirror

1
2
K1(V2−VR−VT )2+α = 12K2(V2−VT )
2+α
VR =
1
2
K2(V2−VT )2+αR
(4.11)
4.3 Building Blocks and Simulations 71
Fig. 4.5 Fully n-type current reference circuit with pseudo p-type current mirror and a
reference resistor
Therefore, we get the overdrive voltage of T2:
Vov2 =VGS2−VT =
1+α
√√√√(2+α)(1− 2+α√K2K1)
K2R
(4.12)
As Vov2 controls the current of T2, the operating current is then fixed. The current can be
expressed as:
Iout =
1
2+α
(2+α)
(
1− 2+α
√
K2
K1
)
2+α√K2R

2+α
1+α
(4.13)
Therefore, the reference current can be designed by choosing the size of T2, the ratio of
W2/W1 and the value of the reference resistor R.
As the circuit also needs all TFTs working in saturation region, we could derive the
working range by applying the saturation conditions. The final working range can be derived
as:
2
3
(Vov2+Vov3)+
1
3
(Vref−VT)< VDD<Vov22 +Vov3+
(Vref+VT)
2
(4.14)
72 TFT analogue circuit building blocks
Fig. 4.6 Simulation results of the current reference circuit with resistor where W3,4 are
simulated with different value to exhibt the change of working range
where Vov2 and Vov3 are the overdrive voltage of T2 and T3. The total working range is then:
Vrange =
1
3
Vov3− 16Vov2+
1
6
Vre f +
5
6
VT (4.15)
Therefore, bigger W2 and smaller W3,4 would be more beneficial in terms of a wider working
range (i.e. bigger Vov3 and smaller Vov2). Here, we choose W1 = 400µm, W2 = 100µm and
R = 600kΩ to yield a current of around 1.5µA, which is a reasonable bias current for a TFT
amplifier stage. Vre f connected to the ground for an easier biasing of the whole circuit.
The circuit is simulated with different W3,4 as shown in Fig. 4.6. The results prove that
a smaller W3,4 value would yield a wider but higher working range. This is consistent with
Eq. 4.14 and 4.15. As can be seen from the figure, the output current is independent of VDD
in a 3-5V range for all the designs.
The above design creates a current reference circuit by replacing the p-type mirror of a
CMOS design. However, we will need to choose a 600kΩ resistor to generate the current.
In many thin-film applications, resistors are not viable as metal track resistors consume too
much area especially for a resistor as big as a few 100kΩ and are not accurately controlled.
Therefore, replacing the resistor with a TFT is more preferable.
As the resistor here is used mainly for its linear I/V relation, it cannot be replaced by a
diode-connected TFT. Therefore, to get a good linearity, the simpliest way is to design a TFT
4.3 Building Blocks and Simulations 73
Fig. 4.7 Fully n-type current reference circuit without resistor
working in linear region. As the resistance of TFT in linear region can be calculated as:
Rlin =
1
K · (VGS−VT )a+1 (4.16)
This is true when VGS >>VDS.
Therefore, to maintain a good linearity, the VGS of the TFT should be fixed with a large
value (i.e. independent of VDD and with a value higher than the voltage at the source of
T1). Among all the nodes in the circuit shown in Fig. 4.6, the gate voltage of T4 meets the
aforementioned requirements. Therefore, the circuit is redesigned as shown in Fig. 4.7. The
resistor is replaced with TR whose gate electrode is connected to the gate of T4.
The size of TR should be chosen to exhibit a resistance of 600kΩ between drain and
source to match the output current with the previous design. The calculation result shows
that the width of TR should be around 29µm.
The simulation of the circuit is done with different WR which is shown in Fig. 4.8. As
illustrated, the circuit still works with a low dependence on VDD. However, the performance
of this circuit is obviously worse than the one with a real resistor. The main reason of this
comes from the small change of T4’s gate voltage (VG4). As the VDD increases, VG4 also
74 TFT analogue circuit building blocks
Fig. 4.8 Simulation results of the current reference circuit without resistor where WR is
simulated with different value to exhibt the change of output current
increases a little due to the none ideality of the devices (i.e. non-infinity output resistance).
Therefore, the resistance of TR will decrease according to Eq. 4.16. This will increase the
output current and thus forms a positive feedback which deteriorate the circuit performance.
In the case where, the performance of the circuit in Fig. 4.7 is accurate enough we should
break the positive feedback that appears on TR. The voltage reference circuit developed
earlier could be used. Thus, the gate voltage of TR can be more stable, thereby, break the
positive feedback loop. The improved circuit schematic is shown in Fig. 4.9. Here, the
voltage reference circuit is connected to the gate of TR making the resistance of TR more
reliable. In fact, as Eq. 4.2 suggests, we could increase β2 to be higher than 2β1+1 making
the output of the voltage inversely related with VDD. Therefore the effect of non-infinity
output resistance could be compensated. Hence, a negative feedback can be formed yielding
a even better performance.
The simulation results of the improved circuit is shown in Fig. 4.10. As can be seen,
output current is much more stable than the previous one and even more stable that the one
with a resistor.
As the negative feedback exists in the new circuit, we have a few more bonuses. One of
them is the sensitivity on the value of WR. As can be seen from Fig. 4.10, even sweeping WR
at 100µm range, the output currents are all stable and with only 1µA change, which in the
previous circuit was achieved with only a few µm change in WR. Therefore, the improved
circuit is more stable against process variations on the size of TR.
4.3 Building Blocks and Simulations 75
Fig. 4.9 Improved current reference circuit with negative feedback on TR
Fig. 4.10 Simulation results of the improved current reference circuit where WR is simulated
with different value to exhibt the change of output current
Another bonus is the VT shift resistance. Although most blocks designed in this section
are VT shift independent, it is not so for the current reference circuit as T1 and T2 are having
different VGS. Therefore, as operation time increases, T1 will become more conductive
compared with T2 and thus increasing the output current (by effectively reducing the value of
76 TFT analogue circuit building blocks
Fig. 4.11 Differential amplifier stage with pseudo p-type mirror
K2
K1
in Eq. 4.13). However, the VT shift of TR will also increase its resistance thus reducing
the output current. Negative feedback also exists in terms of VT shift. Therefore, this more
complicated version of current reference yields better VDD independence and at the same
time better VT shift resistance.
4.3.4 Differential Amplifier
In this section, we consider designing an amplifying stage. With the current mirror designed
in section 4.3.2, we could replicate a CMOS differential stage by replacing the p-type current
mirror. The design is shown in Fig. 4.11. Here, Vre f is connected to ground to optimize the
output range. As the pseudo p-type mirror has big output resistance, the voltage gain of this
differential stage should be the same as that of a real p-type mirror, in the mean time, current
steering feature would also be available thus benefit the gain by an additional factor of 2.
The sizes used for simulation is W3,4 = 50µm, W1,2 = 500µm and W5 = 100µm. T1 and T2
are designed with big W/L ratio for a higher gm. Gate voltage of T5 is set with 3V bias for
a 1.5µA bias current on T5 which matches the design of the current reference circuit in the
previous section.
The transient and ac simulation results are shown in Fig. 4.12. The results suggest that
proposed gain stage have over 40dB or 100 gain within the 3dB bandwidth. This is close to
4.3 Building Blocks and Simulations 77
(a) Transient simulation results of the proposed differential stage with 1mV pp input at 1kHz for 5ms
(b) Gain-phase simulation of the proposed differential stage yielding a 600kHz unit-gain bandwidth
Fig. 4.12 Simulation results of the proposed differential amplifier stage
78 TFT analogue circuit building blocks
Fig. 4.13 Full op-amp design with supply independent bias
the intrinsic gain of the TFT at the working condition demonstrating that the pseudo p-type
current mirror can be used as an promising load in fully n-type circuit design. The gain-phase
simulation suggests a 600kHz unit-gain bandwidth of the stage.
4.4 Full Op-Amp Design
Combining all the building blocks we designed earlier and adding an output stage (which
is a source follower stage), we have the full design of a op-amp which is illustrated in
Fig. 4.13. The output stage is added to improve the driving capability of the circuit by
reducing the output resistance. Simulation result of the proposed op-amp with open circuit
load is illustrated in Fig. 4.14. The op-amp here exhibit a gain of 40dB which benefits from
the high-gain of the differential stage and a unit-gain bandwidth of 300kHz, slightly reduced
compared with the differential pair due to the added stage. The performance here is enough
for many bio-medical applications where signal frequencies are below a few 10kHz. The
output resistance is reduced to 50kΩ making it capable of driving many CMOS circuits.
4.5 Current Mirror Layout and Measurement
In order to evaluate the effectiveness of the circuit design technique, Indium-Silicon-Oxide
(ISO) based current mirrors are fabricated under vacuum process with different layouts. As
will be noted, the layout design could also significantly affect the circuit performance.
4.5 Current Mirror Layout and Measurement 79
(a) Transient simulation results of the proposed op-amp with 1mV pp input at 1kHz for 5ms
(b) Gain-phase simulation of the proposed op-amp yielding a 300kHz unit-gain bandwidth
Fig. 4.14 Simulation results of the proposed op-amp
80 TFT analogue circuit building blocks
Fig. 4.15 Schematic of the fabricated ISO current mirror.
The circuit schematic is illustrated in Fig. 4.15. Assuming a perfect match between the
two transistors, the drain current of T2 (IDS2) would copy the current that flows through the
drain of T1 (IDS1). However, mismatch can happen due to the variance of material properties
and dimensions in the fabrication process. Therefore, we designed two different layout for
the current mirror. The first one is based on two separate devices which is shown in Fig. 4.16a.
As the two devices are located separately, device mismatch would totally be reflected on the
output current.
The current mirror with separate device layout is measured sweeping the voltage supply
at the drain of T1 (VDS1 = VGS) where the drain voltage of T2 (VDS2) is kept at 10V. The
measurement result is illustrated in Fig. 4.16b. As can be seen, the current of the two
transistors are rising according to the increase of VGS. However, there is a mismatch in
current as IDS2 increases slower than IDS1. The normalized current error is between 16% and
32% at a VGS range of 5V to 10V, which is illustrated in the inset of Fig. 4.16b.
The other layout is designed based on the interdigitated stacked layout. The fabricated
layout is shown in Fig. 4.17a. The layout effectively separate each device into 5 devices
connected in parallel. This would average out mismatches between devices and improve
the matching of the overall device. Also, devices are placed adjacent to each other in a
interdigitated way to reduce the mismatch over long distance.
The same measurement is done for a current mirror using the interdigitated stacked layout.
The measurement result is illustrated in Fig. 4.17b where VDS2 is maintained at 10V. As can
be seen, the matching of the transistors is significantly improved. The normalized current
error has been reduced to below 8% at the VGS range of 5 to 10V. This indicates that the
4.5 Current Mirror Layout and Measurement 81
(a) Fabricated current mirror under microscope
(b) Measurement of the fabricated current mirror
Fig. 4.16 Picture and measurement result of the fabricated current mirror based on a separate-
device layout.
82 TFT analogue circuit building blocks
(a) Fabricated current mirror under microscope
(b) Measurement of the fabricated current mirror
Fig. 4.17 Picture and measurement result of the fabricated current mirror based on a interdig-
itated stacked layout.
4.6 Summary and Discussion 83
layout technique used in silicon CMOS technology can be adapted to the vacuum processed
TFTs.
Due to the large mismatch ( 20%) of separate devices, to fabricate a circuit based on
dimension ratios reported in this chapter is very difficult without a specific layout design.
It maybe beneficial to fabricate every device in a multi-finger layout. However, here we
consider the full layout design as a future extension of this dissertation.
4.6 Summary and Discussion
Op-amp is a fundamental building block for any analogue systems. This chapter delves
into the fully n-type circuits with a goal of building a bridge between the underdeveloped
fully n-type TFT circuits and the well developed CMOS circuits. The result here is fruitful.
With the pseudo p-type current mirror, many CMOS design can be converted to fully n-type
designs with comparable performances. The VT independent feature of most building blocks
here also simplifies the VT shift compensation procedure where a clock based compensation
system is not needed.
One noticeable drawback of the pseudo p-type mirror is that the output range is rather
limited compared with the PMOS counterpart. An external reference voltage supply may be
needed in the case when a very wide output range is required. A dynamic reference could
also be designed if another circuit block is added to generate a dynamic Vre f . In terms of
power consumption, the feedback unit adds two more current path which consumes extra
power. Designers should reduce the size of the TFTs used in this block to minimize the
current and hence minimize the power consumption.
The op-amp designed here is a simple version to demonstrate the functionality of all the
building blocks. More stages maybe needed depending on the requirement of applications.
The high gain of the differential stage would effectively reduce the input referred noise
making the existing blocks promising in all kinds of potential applications. The most
outstanding issue remains here is the rail-to-rail output stage. As in this aspect integrated
op-amps mostly benefit from the push-pull architecture which is enabled by complementary
devices, design an output stage with similar performance remains a challenging topic with
fully n-type devices.
Although the design reported in this chapter are all based on n-type devices, they are also
usable in fully p-type designs for example in OTFTs due to the symmetrical nature of the
two types of devices.
The fabrication of the circuit would need a lot of tuning of the layout and models
regarding the variation of parameters. Here, due to the mismatch and especially the difficulty
84 TFT analogue circuit building blocks
of controlling the value of VT , the full circuit fabrication is considered as a future extension
of the research reported in this thesis. We have shown a current mirror stage to illustrate
that 20% error is likely to happen between any two separate TFTs on the same substrate.
Although the matching can be improved to some extent using layout techniques, special
layout is needed for the dimension ratio based circuit designs. Therefore, extensive work is
necessary to achieve a reliable circuit performance.
Chapter 5
Conclusion and Future Work
With the ultimate goal of creating circuits and systems with more functionality, this dis-
sertation has presented the whole process of designing circuits with IGZO TFTs starting
with accurate DC and AC modelling all the way to circuit designs taking into account the
interaction between specific device performances and corresponding alternation of designs.
Physical and empirical models of IGZO TFTs have been successfully implemented in
the Cadence simulation environment with good smoothness and convergence for fast circuit
simulation.
A more precise small signal model for TFTs has been developed taken into account
the non-idealities of TFTs. The proposed model is tested on IGZO TFTs and is potentially
able to work for TFTs from other material families. Because the effects being considered
generally exist in most material families due to the amorphous nature of semiconductors
used in TFTs, although the underlying physics can be different. The proposed model yields
much better accuracy in comparison with widely adapted CMOS small signal model.
Further, we discussed in a general way how TFT performance could affect circuit design
from a device-circuit interaction stand point. Geometric and temperature dependence of
TFT current accuracy are characterised through measurement, statistics and modelling.
Techniques for extraction of defects and ageing in devices using closed-loop feedback are
discussed with their possible extension to other applications.
Finally, fundamental building blocks including voltage and current reference circuits,
pseudo p-type current mirror and differential gain stages are designed using n-type IGZO
TFTs and simulated through the model developed in this dissertation. The op-amp designed
with the aforementioned building blocks are presented for further application-orientated
engineering.
As the dissertation mainly contributes to the device modelling, simulation and mono-type
TFT circuit design, several extensions could be done in the future.
86 Conclusion and Future Work
1. On device modelling, one noticeable improvement could be adding the VT shift model.
This is particularly difficult because the simulation environment would expect a device
performance to be stable especially in AC simulations. More importantly, further study
should be done physically and mathematically on the time-dependent (or real time)
VT model. Although we have mentioned in several chapters the stretched exponential
function of the VT shift, the function has fundamental flaws in circuit simulations due
to the untraceable initial conditions. For example, if we switch on and off a transistor
several times, all the parameters in the stretched exponential function (i.e. β and τ)
would and should change. However, modelling β and τ based on switching events is
very difficult if not impossible. Preliminary work along the line have been reported [?
], although there is room for refinement if thermodynamic considerations are brought
into the picture.
2. Several other circuit building blocks could be designed to expand the library of ana-
logue building blocks. One of which is a rail-to-rail output stage. As class AB
amplifier needs complementary devices to work, it will be meaningful to achieve a
similar performance with mono-type TFTs.
3. The temperature dependence of circuit blocks was not compensated in the designs
presented. Therefore, another meaningful improvement is to design a temperature
independent circuit, in particular, a temperature independent reference circuit.
References
[1] A. Nathan, A. Ahnood, M. T. Cole, S. Lee, Y. Suzuki, P. Hiralal, F. Bonaccorso,
T. Hasan, L. Garcia-Gancedo, A. Dyadyusha, S. Haque, P. Andrew, S. Hofmann,
J. Moultrie, D. Chu, A. J. Flewitt, A. C. Ferrari, M. J. Kelly, J. Robertson, G. A. J.
Amaratunga, and W. I. Milne, “Flexible electronics: The next ubiquitous platform,” in
Proceedings of the IEEE, vol. 100, pp. 1486–1517, 2012.
[2] F.-g. Structure, T. Yokota, T. Sekitani, T. Tokuhara, N. Take, U. Zschieschang,
M. Takamiya, T. Sakurai, and T. Someya, “Sheet-Type Flexible Organic Active Matrix
Amplifier System Using Pseudo-CMOS Circuits With,” vol. 59, no. 12, pp. 3434–3441,
2012.
[3] H. Marien, M. S. J. Steyaert, E. Van Veenendaal, and P. Heremans, “A fully integrated
sigma-delta ADC in organic thin-film transistor technology on flexible plastic foil,” in
IEEE Journal of Solid-State Circuits, vol. 46, pp. 276–284, 2011.
[4] L. Zhou, A. Wanga, S.-C. Wu, J. Sun, S. Park, and T. N. Jackson, “All-organic active
matrix flexible display,” Applied Physics Letters, vol. 88, p. 083502, feb 2006.
[5] D.-U. Jin, J.-S. Lee, T.-W. Kim, S.-G. An, D. Straykhilev, Y.-S. Pyo, H.-S. Kim,
D.-B. Lee, Y.-G. Mo, H.-D. Kim, and H.-K. Chung, “65.2: Distinguished Paper:
World-Largest (6.5”) Flexible Full Color Top Emission AMOLED Display on Plastic
Film and Its Bending Properties,” SID Symposium Digest of Technical Papers, vol. 40,
no. 1, p. 983, 2009.
[6] S.-H. K. Park, M. Ryu, C.-S. Hwang, S. Yang, C. Byun, J.-I. Lee, J. Shin, S. M. Yoon,
H. Y. Chu, K. I. Cho, K. Lee, M. S. Oh, and S. Im, “42.3: Transparent ZnO Thin Film
Transistor for the Application of High Aperture Ratio Bottom Emission AM-OLED
Display,” SID Symposium Digest of Technical Papers, vol. 39, no. 1, p. 629, 2008.
[7] C. Zysset, N. Munzenrieder, L. Petti, L. Buthe, G. A. Salvatore, and G. Troster, “IGZO
TFT-Based All-Enhancement Operational Amplifier Bent to a Radius of 5 mm,” IEEE
Electron Device Letters, vol. 34, pp. 1394–1396, nov 2013.
[8] T. Tanaka, H. Asuma, K. Ogawa, Y. Shinagawa, K. Ono, and N. Konishi, “An LCD
addressed by a-Si:H TFTs with peripheral poly-Si TFT circuits,” Proceedings of IEEE
International Electron Devices Meeting, 1993.
[9] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-
temperature fabrication of transparent flexible thin-film transistors using amorphous
oxide semiconductors.,” Nature, vol. 432, pp. 488–492, 2004.
88 References
[10] D. Gundlach, Y. Lin, T. Jackson, S. Nelson, and D. Schlom, “Pentacene organic
thin-film transistors-molecular ordering and mobility,” IEEE Electron Device Letters,
vol. 18, 1997.
[11] R. M. A. Dawson and M. G. Kane, “24.1: Invited Paper: Pursuit of Active Matrix
Organic Light Emitting Diode Displays,” SID Symposium Digest of Technical Papers,
vol. 32, no. 1, p. 372, 2001.
[12] V. Fiore, E. Ragonese, S. Abdinia, S. Jacob, I. Chartier, R. Coppard, A. Van Roermund,
E. Cantatore, and G. Palmisano, “30.4 A 13.56MHz RFID tag with active envelope
detection in an organic complementary TFT technology,” in Digest of Technical Papers
- IEEE International Solid-State Circuits Conference, vol. 57, pp. 492–493, 2014.
[13] G. Maiellaro, E. Ragonese, R. Gwoziecki, S. Jacobs, N. Marjanovic, M. Chrapa,
J. Schleuniger, and G. Palmisano, “Ambient light organic sensor in a printed com-
plementary organic TFT technology on flexible plastic foil,” IEEE Transactions on
Circuits and Systems I: Regular Papers, vol. 61, pp. 1036–1043, 2014.
[14] K. Y. Chung and G. W. Neudeck, “Transient analysis of the CMOS-like a-SI:H TFT
inverter circuit,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 822–829, 1989.
[15] C. Zysset, N. Munzenrieder, T. Kinkeldei, K. Cherenack, and G. Troster, “Indium-
gallium-zinc-oxide based mechanically flexible transimpedance amplifier,” Electronics
Letters, vol. 47, no. 12, p. 691, 2011.
[16] T. Brody, “The thin film transistor-A late flowering bloom,” IEEE Transactions on
Electron Devices, vol. 31, pp. 1614–1628, nov 1984.
[17] S. Lee and A. Nathan, “Subthreshold Schottky-barrier thin-film transistors with ul-
tralow power and high intrinsic gain,” Science, vol. 354, no. 6310, pp. 302–304,
2016.
[18] M. S. Shur, “SPICE Models for Amorphous Silicon and Polysilicon Thin Film Tran-
sistors,” Journal of The Electrochemical Society, vol. 144, no. 8, p. 2833, 1997.
[19] R. Chaji and A. Nathan, Thin Film Transistor Circuits and Systems. Cambridge
University Press, 2013.
[20] S. Lee, S. Jeon, R. Chaji, and A. Nathan, “Transparent semiconducting oxide technol-
ogy for touch free interactive flexible displays,” Proceedings of the IEEE, vol. 103,
no. 4, pp. 644–664, 2015.
[21] S. Jeon, I. Song, S. Lee, B. Ryu, S. E. Ahn, E. Lee, Y. Kim, A. Nathan, J. Robertson,
and U. I. Chung, “Origin of high photoconductive gain in fully transparent hetero-
junction nanocrystalline oxide image sensors and interconnects,” Advanced Materials,
vol. 26, no. 41, pp. 7102–7109, 2014.
[22] A. Nathan, S. Lee, S. Jeon, I. Song, and U.-i. Chung, “Amorphous Oxide TFTs:
Progress and Issues,” SID Symposium Digest of Technical Papers information display,
vol. 43, no. 1, pp. 1–4, 2012.
References 89
[23] H. Aoki, “Dynamic characterization of a-Si TFT-LCD pixels,” IEEE Transactions on
Electron Devices, vol. 43, no. 1, pp. 31–39, 1996.
[24] K. Karim, P. Servati, N. Mohan, A. Nathan, and J. Rowlands, “VHDL-AMS modeling
and simulation of a passive pixel sensor in a-Si:H technology for medical imaging,” in
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat.
No.01CH37196), vol. 5, pp. 479–482, IEEE.
[25] K. Khakzar and E. Lueder, “Modeling of amorphous-silicon thin-film transistors for
circuit simulations with SPICE,” IEEE Transactions on Electron Devices, vol. 39,
pp. 1428–1434, jun 1992.
[26] L. Resendiz, B. Iniguez, a. Estrada, and a. Cerdeira, “Modification of amorphous level
15 AIM SPICE model to include new subthreshold model,” 2004 24th International
Conference on Microelectronics (IEEE Cat. No.04TH8716), vol. 1, pp. 16–19, 2004.
[27] T. Leroux, “Static and dynamic analysis of amorphous-silicon field-effect transistors,”
Solid-State Electronics, vol. 29, pp. 47–58, jan 1986.
[28] M. Shur, M. Hack, and J. G. Shaw, “A new analytic model for amorphous silicon
thin-film transistors,” Journal of Applied Physics, vol. 66, no. 7, p. 3371, 1989.
[29] G. Horowitz and P. Delannoy, “An analytical model for organic-based thin-film
transistors,” Journal of Applied Physics, vol. 70, no. 1, p. 469, 1991.
[30] M. C. J. M. Vissenberg and M. Matters, “Theory of the field-effect mobility in
amorphous organic transistors,” vol. 57, no. 20, p. 13, 1998.
[31] M. Estrada, A. Cerdeira, J. Puigdollers, L. Reséndiz, J. Pallares, L. Marsal, C. Voz,
and B. Iñiguez, “Accurate modeling and parameter extraction method for organic
TFTs,” Solid-State Electronics, vol. 49, pp. 1009–1016, jun 2005.
[32] M. Fadlallah, W. Benzarti, G. Billiot, W. Eccleston, and D. Barclay, “Modeling and
characterization of organic thin film transistors for circuit design,” Journal of Applied
Physics, vol. 99, no. 10, p. 104504, 2006.
[33] A. Valletta, A. S. Demirkol, G. Maira, M. Frasca, V. Vinciguerra, L. G. Occhipinti,
L. Fortuna, L. Mariucci, and G. Fortunato, “A compact Spice model for organic TFTs
and applications to logic circuit design,” in 2015 IEEE 15th International Conference
on Nanotechnology (IEEE-NANO), pp. 1434–1437, IEEE, jul 2015.
[34] H.-H. Hsieh, T. Kamiya, K. Nomura, H. Hosono, and C.-C. Wu, “Modeling of
amorphous InGaZnO[sub 4] thin film transistors and their subgap density of states,”
Applied Physics Letters, vol. 92, no. 13, p. 133503, 2008.
[35] S. Lee, K. Ghaffarzadeh, A. Nathan, J. Robertson, S. Jeon, C. Kim, I. H. Song, and
U. I. Chung, “Trap-limited and percolation conduction mechanisms in amorphous
oxide semiconductor thin film transistors,” Applied Physics Letters, vol. 98, 2011.
[36] S. Lee, S. Jeon, and A. Nathan, “Modeling Sub-Threshold Current–Voltage Character-
istics in Thin Film Transistors,” Journal of Display Technology, vol. 9, pp. 883–889,
nov 2013.
90 References
[37] S. Lee and A. Nathan, “Localized tail state distribution in amorphous oxide transistors
deduced from low temperature measurements,” Applied Physics Letters, vol. 101,
no. 11, p. 113502, 2012.
[38] S. Lee, D. Striakhilev, S. Jeon, and A. Nathan, “Unified Analytic Model for Cur-
rent–Voltage Behavior in Amorphous Oxide Semiconductor TFTs,” IEEE Electron
Device Letters, vol. 35, pp. 84–86, jan 2014.
[39] Z. Zong, L. Li, J. Jang, N. Lu, and M. Liu, “Analytical surface-potential compact
model for amorphous-IGZO thin-film transistors,” Journal of Applied Physics, vol. 117,
no. 21, p. 215705, 2015.
[40] C. Perumal, K. Ishida, R. Shabanpour, B. K. Boroujeni, L. Petti, N. S. Munzenrieder,
G. A. Salvatore, C. Carta, G. Troster, and F. Ellinger, “A compact a-IGZO TFT model
based on MOSFET SPICE Level=3 template for Analog/RF circuit designs,” IEEE
Electron Device Letters, vol. 34, no. 11, pp. 1391–1393, 2013.
[41] A. a. Fomani and A. Nathan, “Metastability mechanisms in thin film transistors
quantitatively resolved using post-stress relaxation of threshold voltage,” Journal of
Applied Physics, vol. 109, no. 8, p. 084521, 2011.
[42] G. Horowitz, “Organic Field-Effect Transistors,” Advanced Materials, vol. 10, pp. 365–
377, mar 1998.
[43] C. H. Kim, A. Castro-Carranza, M. Estrada, A. Estrada, Y. Horowitz, G. Horowitz,
and B. Iniguez, “A compact model for organic field-effect transistors with improved
output asymptotic behaviors,” IEEE Transactions on Electron Devices, vol. 60, no. 3,
pp. 1136–1141, 2013.
[44] L. L. L. Li, H. Marien, J. Genoe, M. Steyaert, and P. Heremans, “Compact Model
for Organic Thin-Film Transistor,” IEEE Electron Device Letters, vol. 31, no. 3,
pp. 210–212, 2010.
[45] S. Lee, Y. Yang, and A. Nathan, “Modeling Above-Threshold Current-Voltage Char-
acteristics in Oxide TFTs for Display Pixel Circuits,” Digest of Technical papers,
International Symposium, Display Week 2013, SID (Society for Information Display)
Symposium, vol. 44, no. 1, pp. 22–25, 2013.
[46] “IEEE Recommended Practices #P1485 on: Test Procedures for
Micro-electronic MOSFET Circuit Simulator Model Validation.”
http://electronica.ugr.es/˜amroldan/modulos/investiga/material_restringido/estandar_medida_mos.pdf,
1997.
[47] G. H. See, X. Zhou, K. Chandrasekaran, S. B. Chiah, Z. Zhu, C. Wei, S. Lin, G. Zhu,
and G. H. Lim, “A compact model satisfying Gummel symmetry in higher order
derivatives and applicable to asymmetric MOSFETs,” IEEE Transactions on Electron
Devices, vol. 55, no. 2, pp. 624–631, 2008.
[48] L. W. Nagel and D. O. Pederson, “SPICE (Simulation Program with Integrated Circuit
Emphasis),” No ERLM382Electronic Research Laboratory, vol. Memorandum, pp. 1–
4, 1973.
References 91
[49] B. Sheu, D. Scharfetter, P.-K. Ko, and M.-C. Jeng, “BSIM: Berkeley short-channel
IGFET model for MOS transistors,” 1987.
[50] IEEE, Verilog IEEE Std 1364-1995. 1996.
[51] H. Verilog, “Verilog-AMS Language Reference Manual,” Eda-Stds.Org, 2014.
[52] L. Lemaitre, C. McAndrew, and S. Hamm, “ADMS-automatic device model synthe-
sizer,” Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat.
No.02CH37285), pp. 27–30, 2002.
[53] L. Lemaitre, G. Coram, C. McAndrew, and K. Kundert, “Extensions to Verilog-A
to support compact device modeling,” Proceedings of the 2003 IEEE International
Workshop on Behavioral Modeling and Simulation, 2003.
[54] M. A. Chalkiadaki, C. Valla, F. Poullet, and M. Bucher, “Why- and how- to integrate
Verilog-A compact models in SPICE simulators,” International Journal of Circuit
Theory and Applications, vol. 41, no. July 2012, pp. 1203–1211, 2013.
[55] G. Depeyrot, “Verilog-A Compact Model Coding Whitepaper,” Memory, vol. 2,
no. June, pp. 821– 824, 2010.
[56] A. S. Sedra and K. C. Smith, Microelectronic circuits. New York Oxford University
Press, 6th ed., 2011.
[57] M. Powell, “The physics of amorphous-silicon thin-film transistors,” IEEE Transac-
tions on Electron Devices, vol. 36, no. 12, pp. 2753–2763, 1989.
[58] P. Servati, D. Striakhilev, and A. Nathan, “Above-threshold parameter extraction and
modeling for amorphous silicon thin-film transistors,” IEEE Transactions on Electron
Devices, vol. 50, pp. 2227–2235, nov 2003.
[59] P. V. Necliudov, M. S. Shur, D. J. Gundlach, and T. N. Jackson, “Modeling of organic
thin film transistors of different designs,” Journal of Applied Physics, vol. 88, no. 11,
p. 6594, 2000.
[60] H. Klauk, G. Schmid, W. Radlik, W. Weber, L. S. Zhou, C. D. Sheraw, J. A. Nichols,
and T. N. Jackson, “Contact resistance in organic thin film transistors,” Solid-State
Electron., vol. 47, pp. 297–301, 2003.
[61] P. V. Necliudov, M. S. Shur, D. J. Gundlach, and T. N. Jackson, “Contact resistance
extraction in pentacene thin film transistors,” Solid-State Electronics, vol. 47, pp. 259–
262, feb 2003.
[62] M. J. Powell, C. van Berkel, and J. R. Hughes, “Time and temperature dependence of
instability mechanisms in amorphous silicon thin-film transistors,” Applied Physics
Letters, vol. 54, no. 14, p. 1323, 1989.
[63] S. J. Zilker, C. Detcheverry, E. Cantatore, and D. M. De Leeuw, “Bias stress in
organic thin-film transistors and logic gates,” Applied Physics Letters, vol. 79, no. 8,
pp. 1124–1126, 2001.
92 References
[64] H.-W. Zan and S.-C. Kao, “The Effects of Drain-Bias on the Threshold Voltage
Instability in Organic TFTs,” IEEE Electron Device Letters, vol. 29, pp. 155–157, feb
2008.
[65] S. Lee, A. Nathan, S. Jeon, and J. Robertson, “Oxygen Defect-Induced Metastability
in Oxide Semiconductors Probed by Gate Pulse Spectroscopy,” Scientific Reports,
vol. 5, no. October, p. 14902, 2015.
[66] R. B. M. Cross and M. M. De Souza, “Investigating the stability of zinc oxide thin
film transistors,” Applied Physics Letters, vol. 89, no. 26, p. 263513, 2006.
[67] J. Brittain, “Thevenin’s theorem,” IEEE Spectrum, vol. 27, p. 42, mar 1990.
[68] D. H. Johnson, “Origins of the equivalent circuit concept: The current-source equiva-
lent,” 2003.
[69] S. Sambandan and A. Nathan, “A stable n-channel mirrorable current source for
versatile analog design with thin film transistors,” in 48th Midwest Symposium on
Circuits and Systems, 2005., pp. 836–839 Vol. 1, IEEE, 2005.
[70] L. Toledo, C. Dualibe, P. Petrashin, and W. Lancioni, “A novel supply-independent
biasing scheme for use in CMOS voltage reference,” in Proc. Design of Circuits and
Integrated Systems (DCIS), (Lisbon, Portugal), 2005.
[71] E. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion
operations,” IEEE Journal of Solid-State Circuits, vol. 12, pp. 224–231, jun 1977.
[72] S. Sambandan and A. Nathan, “Equivalent Circuit Description of Threshold Voltage
Shift in a-Si:H TFTs From a Probabilistic Analysis of Carrier Population Dynamics,”
IEEE Transactions on Electron Devices, vol. 53, pp. 2306–2311, sep 2006.
[73] H. Klauk, “Organic thin-film transistors,” Chemical Society Reviews, vol. 39, no. 7,
p. 2643, 2010.
[74] L. Feng, W. Tang, X. Xu, Q. Cui, and X. Guo, “Ultralow-Voltage Solution-Processed
Organic Transistors With Small Gate Dielectric Capacitance,” IEEE Electron Device
Letters, vol. 34, pp. 129–131, jan 2013.
[75] Jae Sang Lee, Seongpil Chang, Sang-Mo Koo, and Sang Yeol Lee, “High-Performance
a-IGZO TFT With ZrO2 Gate Dielectric Fabricated at Room Temperature,” IEEE
Electron Device Letters, vol. 31, pp. 225–227, mar 2010.
[76] J.-S. Park, J. K. Jeong, Y.-G. Mo, H. D. Kim, and S.-I. Kim, “Improvements in the
device characteristics of amorphous indium gallium zinc oxide thin-film transistors by
Ar plasma treatment,” Applied Physics Letters, vol. 90, no. 26, p. 262106, 2007.
[77] D. Braga and G. Horowitz, “High-Performance organic field-effect transistors,” 2009.
[78] X. Guo and S. R. P. Silva, “ENGINEERING: High-Performance Transistors by Design,”
Science, vol. 320, pp. 618–619, may 2008.
[79] C. Dimitrakopoulos and P. Malenfant, “Organic thin film transistors for large area
electronics,” Advanced Materials, vol. 14, no. 2, pp. 99–117, 2002.
References 93
[80] S.-J. Kim, S.-Y. Lee, Y. W. Lee, S.-H. Kuk, J.-Y. Kwon, and M.-K. Han, “Effect of
Charge Trapping/Detrapping on Threshold Voltage Shift of IGZO TFTs under AC
Bias Stress,” Electrochemical and Solid-State Letters, vol. 15, no. 4, p. H108, 2012.
[81] A. Suresh and J. F. Muth, “Bias stress stability of indium gallium zinc oxide chan-
nel based transparent thin film transistors,” Applied Physics Letters, vol. 92, no. 3,
p. 033502, 2008.
[82] Y. Qiu, Y. Hu, G. Dong, L. Wang, J. Xie, and Y. Ma, “H[sub 2]O effect on the stability
of organic thin-film field-effect transistors,” Applied Physics Letters, vol. 83, no. 8,
p. 1644, 2003.
[83] K. H. Ji, J.-I. Kim, Y.-G. Mo, J. H. Jeong, S. Yang, C.-S. Hwang, S.-H. K. Park, M.-K.
Ryu, S.-Y. Lee, and J. K. Jeong, “Comparative Study on Light-Induced Bias Stress
Instability of IGZO Transistors With SiNx and SiO2,” IEEE Electron Device Letters,
vol. 31, pp. 1404–1406, dec 2010.
[84] H. Marien, M. Steyaert, E. van Veenendaal, and P. Heremans, “Analog techniques
for reliable organic circuit design on foil applied to an 18dB single-stage differential
amplifier,” Organic Electronics, vol. 11, pp. 1357–1362, aug 2010.
[85] S. Jeon, S.-E. Ahn, I. Song, C. J. Kim, U.-I. Chung, E. Lee, I. Yoo, A. Nathan, S. Lee,
J. Robertson, and K. Kim, “Gated three-terminal device architecture to eliminate
persistent photoconductivity in oxide semiconductor photosensor arrays,” Nature
Materials, vol. 11, no. 4, pp. 301–305, 2012.
[86] S. Sambandan, “High-gain amplifiers with amorphous-silicon thin-film transistors,”
IEEE Electron Device Letters, vol. 29, pp. 882–884, 2008.
[87] P. Bahubalindruni, V. G. Tavares, P. G. De Oliveira, P. Barquinha, R. Martins, and
E. Fortunato, “High-gain amplifier with n-type transistors,” 2013 IEEE International
Conference of Electron Devices and Solid-State Circuits, EDSSC 2013, vol. 2, no. 2,
2013.
[88] Y.-C. Tarn, P.-C. Ku, H.-H. Hsieh, and L.-H. Lu, “An Amorphous-Silicon Operational
Amplifier and Its Application to a 4-Bit Digital-to-Analog Converter,” IEEE Journal
of Solid-State Circuits, vol. 45, pp. 1028–1035, may 2010.
[89] X. Cheng, S. Lee, G. Yao, and A. Nathan, “TFT Compact Modeling,” Journal of
Display Technology, vol. 12, pp. 898–906, sep 2016.
[90] O. Marinov, M. J. Deen, U. Zschieschang, and H. Klauk, “Organic thin-film transistors:
Part I-compact DC modeling,” IEEE Transactions on Electron Devices, vol. 56, no. 12,
pp. 2952–2961, 2009.
[91] G. R. Chaji, S. Alexander, J. Marcel Dionne, Y. Azizi, C. Church, J. Hamer, J. Spindler,
and A. Nathan, “Stable RGBW AMOLED display with OLED degradation compen-
sation using electrical feedback,” Digest of Technical Papers - IEEE International
Solid-State Circuits Conference, vol. 53, no. 3, pp. 118–119, 2010.
94 References
[92] J. K. Jeong, J. H. Jeong, J. H. Choi, J. S. Im, S. H. Kim, H. W. Yang, K. N. Kang, K. S.
Kim, T. K. Ahn, H.-J. Chung, M. Kim, B. S. Gu, J.-S. Park, Y.-G. Mo, H. D. Kim, and
H. K. Chung, “3.1: Distinguished Paper: 12.1-Inch WXGA AMOLED Display Driven
by Indium-Gallium-Zinc Oxide TFTs Array,” SID Symposium Digest of Technical
Papers, vol. 39, no. 1, p. 1, 2008.
[93] J.-H. Lee, W.-J. Nam, S.-H. Jung, and M.-K. Han, “A New Current Scaling Pixel
Circuit for AMOLED,” IEEE Electron Device Letters, vol. 25, pp. 280–282, may
2004.
[94] M. Bagheri, X. Cheng, J. Zhang, S. Lee, S. Ashtiani, and A. Nathan, “Threshold
Voltage Compensation Error in Voltage Programmed AMOLED Displays,” Journal of
Display Technology, vol. 12, pp. 658–664, jun 2016.
[95] S. Lee and A. Nathan, “Conduction Threshold in Accumulation-Mode InGaZnO Thin
Film Transistors,” Scientific Reports, vol. 6, no. October 2015, p. 22567, 2016.
[96] A. Nathan, G. R. Chaji, and S. J. Ashtiani, “Driving schemes for a-Si and LTPS
AMOLED displays,” IEEE/OSA Journal of Display Technology, vol. 1, no. 2, pp. 267–
277, 2005.
[97] Y. Lin, H.-P. Shieh, and J. Kanicki, “A Novel Current-Scaling a-Si:H TFTs Pixel
Electrode Circuit for AM-OLEDs,” IEEE Transactions on Electron Devices, vol. 52,
pp. 1123–1131, jun 2005.
[98] Y.-C. Lin and H.-P. Shieh, “A Novel Current Memory Circuit for AMOLEDs,” IEEE
Transactions on Electron Devices, vol. 51, pp. 1037–1040, jun 2004.
[99] M. Ohta, H. Tsutsu, H. Takahara, I. Kobayashi, T. Uemura, and Y. Takubo, “9.4: A
Novel Current Programmed Pixel for Active Matrix OLED Displays,” SID Symposium
Digest of Technical Papers, vol. 34, no. 1, p. 108, 2003.
[100] T. Sasaoka, M. Sekiya, A. Yumoto, J. Yamada, T. Hirano, Y. Iwase, T. Yamada,
T. Ishibashi, T. Mori, M. Asano, S. Tamura, and T. Urabe, “24.4L: Late-News Paper:
A 13.0-inch AM-OLED Display with Top Emitting Structure and Adaptive Current
Mode Programmed Pixel Circuit (TAC),” SID Symposium Digest of Technical Papers,
vol. 32, no. 1, p. 384, 2001.
[101] S. Ashtiani, P. Servati, D. Striakhilev, and A. Nathan, “A 3-TFT Current-Programmed
Pixel Circuit for AMOLEDs,” IEEE Transactions on Electron Devices, vol. 52,
pp. 1514–1518, jul 2005.
[102] K. Sakariya, P. Servati, and A. Nathan, “Stability Analysis of Current Programmed
a-Si:H AMOLED Pixel Circuits,” IEEE Transactions on Electron Devices, vol. 51,
pp. 2019–2025, dec 2004.
[103] J. Yamashita, K. Uchino, T. Yamamoto, T. Sasaoka, and T. Urabe, “44.2: New
Driving Method with Current Subtraction Pixel Circuit for AM-OLED Displays,” SID
Symposium Digest of Technical Papers, vol. 36, no. 1, p. 1452, 2005.
References 95
[104] G. Chaji and A. Nathan, “Low-Power Low-Cost Voltage-Programmed a-Si:H
AMOLED Display for Portable Devices,” Journal of Display Technology, vol. 4,
pp. 233–237, jun 2008.
[105] S.-H. Jung, W.-J. Nam, and M.-k. Han, “P-104: A New Voltage Modulated AMOLED
Pixel Design Compensating Threshold Voltage Variation of Poly-Si TFTs,” SID Sym-
posium Digest of Technical Papers, vol. 33, no. 1, p. 622, 2002.
[106] Joon-Chul Goh, Hoon-Ju Chung, Jin Jang, and Chul-Hi Han, “A new pixel circuit for
active matrix organic light emitting diodes,” IEEE Electron Device Letters, vol. 23,
pp. 544–546, sep 2002.
[107] S.-M. Choi, O.-K. Kwon, and H.-K. Chung, “P-11: An Improved Voltage Programmed
Pixel Structure for Large Size and High Resolution AM-OLED Displays,” SID Sym-
posium Digest of Technical Papers, vol. 35, no. 1, p. 260, 2004.
[108] Jae-Hoon Lee, Ji-Hoon Kim, and Min-Koo Han, “A new a-Si:H TFT pixel circuit
compensating the threshold voltage shift of a-Si:H TFT and OLED for active matrix
OLED,” IEEE Electron Device Letters, vol. 26, pp. 897–899, dec 2005.
[109] Y.-H. Tai, B.-T. Chen, Y.-J. Kuo, C.-C. Tsai, K.-Y. Chiang, Y.-J. Wei, and H.-C. Cheng,
“A New Pixel Circuit for Driving Organic Light-Emitting Diode With Low Temperature
Polycrystalline Silicon Thin-Film Transistors,” Journal of Display Technology, vol. 1,
pp. 100–104, sep 2005.
[110] Y. Matsueda, R. Kakkad, Y. S. Park, H. H. Yoon, W. P. Lee, J. B. Koo, and H. K.
Chung, “35.1: 2.5-in. AMOLED with Integrated 6-Bit Gamma Compensated Digital
Data Driver,” SID Symposium Digest of Technical Papers, vol. 35, no. 1, p. 1116,
2004.
[111] C.-L. Lin and T.-T. Tsai, “A Novel Voltage Driving Method Using 3-TFT Pixel Circuit
for AMOLED,” IEEE Electron Device Letters, vol. 28, pp. 489–491, jun 2007.
[112] J. L. Sanford and F. R. Libsch, “4.2: TFT AMOLED Pixel Circuits and Driving
Methods,” SID Symposium Digest of Technical Papers, vol. 34, no. 1, p. 10, 2003.
[113] M. Bagheri, S. Ashtiani, and A. Nathan, “Fast voltage-programmed pixel architecture
for AMOLED displays,” Journal of Display Technology, vol. 6, no. 5, pp. 191–195,
2010.
[114] H. J. In and O. K. Kwon, “External compensation of non-uniform electrical character-
istics of thin-film transistors and degradation of OLED devices in AMOLED displays,”
IEEE Electron Device Letters, vol. 30, no. 4, pp. 377–379, 2009.
[115] S. Jafarabadiashtiani, G. Chaji, S. Sambandan, D. Striakhilev, A. Nathan, and P. Ser-
vati, “P-25: A New Driving Method for a-Si AMOLED Displays Based on Voltage
Feedback,” SID Symposium Digest of Technical Papers, vol. 36, no. 1, p. 316, 2005.
[116] J. H. Baek, M. Lee, J. H. Lee, H. S. Pae, C. J. Lee, J. T. Kim, C. S. Choi, H. K. Kim,
T. J. Kim, and H. K. Chung, “A Current-Mode Display Driver IC Using Sample-and-
Hold Scheme for QVGA Full-Color AMOLED Displays,” IEEE Journal of Solid-State
Circuits, vol. 41, pp. 2974–2982, dec 2006.
96 References
[117] S. J. Ashtiani and A. Nathan, “A Driving Scheme for Active-Matrix Organic Light-
Emitting Diode Displays Based on Current Feedback,” Journal of Display Technology,
vol. 5, pp. 257–264, jul 2009.
[118] H.-J. In, B.-D. Choi, H.-K. Chung, and O.-K. Kwon, “Current-Sensing and Voltage-
Feedback Driving Method for Large-Area High-Resolution Active Matrix Organic
Light Emitting Diodes,” Japanese Journal of Applied Physics, vol. 45, pp. 4396–4401,
may 2006.
[119] H.-J. In, P.-S. Kwag, J.-S. Kang, O.-K. Kwon, and H.-K. Chung, “Voltage-
programming method with transimpedance-feedback technique for threshold voltage
and mobility compensations in large-area high-resolution AMOLED displays,” Jour-
nal of the Society for Information Display, vol. 14, no. 8, p. 665, 2006.
[120] R. Itou, M. Kayama, and T. Shima, “Some analog building blocks for TFT circuits,”
in Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems.
MWSCAS 2001 (Cat. No.01CH37257), vol. 1, pp. 417–420, IEEE, 2001.
[121] P. R. Gray, P. Hurst, R. G. Meyer, and S. Lewis, Analysis and design of analog
integrated circuits. Wiley, 2001.
[122] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing.
New York: Wiley-Interscience, 1 ed., 1986.
[123] Y. Tsividis, D. Fraser, and J. Dziak, “A process-insensitive high-performance NMOS
operational amplifier,” IEEE Journal of Solid-State Circuits, vol. 15, pp. 921–928, dec
1980.
[124] D. Senderowicz, D. Hodges, and P. Gray, “High-performance NMOS operational
amplifier,” IEEE Journal of Solid-State Circuits, vol. 13, pp. 760–766, dec 1978.
[125] M. J. Seok, M. H. Choi, M. Mativenga, D. Geng, D. Y. Kim, and J. Jang, “A Full-
Swing a-IGZO TFT-Based Inverter With a Top-Gate-Bias-Induced Depletion Load,”
IEEE Electron Device Letters, vol. 32, pp. 1089–1091, aug 2011.
[126] B. Kim, C.-I. Ryoo, S.-J. Kim, J.-U. Bae, H.-S. Seo, C.-D. Kim, and M.-K. Han, “New
Depletion-Mode IGZO TFT Shift Register,” IEEE Electron Device Letters, vol. 32,
pp. 158–160, feb 2011.
[127] D. Heineck, B. McFarlane, and J. Wager, “Zinc Tin Oxide Thin-Film-Transistor
Enhancement/Depletion Inverter,” IEEE Electron Device Letters, vol. 30, pp. 514–516,
may 2009.
[128] H. Ma, R. W. R. Wallbank, R. Chaji, J. Li, Y. Suzuki, C. Jiggins, and A. Nathan, “An
impedance-based integrated biosensor for suspended DNA characterization,” Scientific
Reports, vol. 3, p. 2730, 2013.
[129] K. Takechi, S. Iwamatsu, S. Konno, T. Yahagi, Y. Abe, M. Katoh, and H. Tanabe,
“Demonstration of Detecting Small pH Changes Using High-Sensitivity Amorphous
InGaZnO 4 Thin-Film Transistor pH Sensor System,” IEEE Transactions on Electron
Devices, vol. 64, pp. 638–641, feb 2017.
References 97
[130] M. Barron, “Low level currents in insulated gate field effect transistors,” Solid-State
Electronics, vol. 15, pp. 293–302, 1972.
[131] R. M. Swanson and J. D. Meindl, “Ion-implanted complementary mos transistors in
low-voltage circuits,” IEEE Journal of Solid-State Circuits, vol. 7, no. 2, pp. 146–153,
1972.
[132] R. Barker, “Small-signal subthreshold model for i.g.f.e.t.s,” Electronics Letters, vol. 12,
p. 260, may 1976.
[133] E. Fortunato, P. Barquinha, and R. Martins, “Oxide semiconductor thin-film transistors:
A review of recent advances,” 2012.
[134] T. Sekitani, U. Zschieschang, H. Klauk, and T. Someya, “Flexible organic transistors
and circuits with extreme bending stability.,” Nature materials, vol. 9, no. 12, pp. 1015–
1022, 2010.
[135] S. M. Sze and K. K. Ng, Physics of semiconductor devices. 2006.
[136] Y. Nishi, “Insulated gate field effect transistor and its manufacturing method,” Japan
Patent, vol. 587, no. 527, pp. 162–165, 1970.
[137] M. P. Lefselter and S. M. Sze, “SB-IGFET: An Insulated-Gate Field-Effect Transistor
Using Schottky Barrier Contacts for Source and Drain,” Proceedings of the IEEE,
vol. 56, no. 8, pp. 1400–1402, 1968.
[138] J. M. Shannon and F. Balon, “Source-gated thin-film transistors,” Solid-State Electron-
ics, vol. 52, no. 3, pp. 449–454, 2008.
[139] D. Sarkar, X. Xie, W. Liu, W. Cao, J. Kang, Y. Gong, S. Kraemer, P. M. Ajayan, and
K. Banerjee, “A subthermionic tunnel field-effect transistor with an atomically thin
channel,” Nature, vol. 526, no. 7571, pp. 91–95, 2015.
[140] T. T. Trinh, K. Jang, V. A. Dao, and J. Yi, “Effect of high conductivity amorphous
InGaZnO active layer on the field effect mobility improvement of thin film transistors,”
Journal of Applied Physics, vol. 116, p. 214504, dec 2014.
[141] Y. Xu, H. Sun, and Y.-Y. Noh, “Schottky Barrier in Organic Transistors,” IEEE
Transactions on Electron Devices, vol. 64, pp. 1932–1943, may 2017.

Appendix A
Device Circuit Interaction
A.1 Importance of DCI in TFTs
Although the ever-evolving TFT technology continues to produce devices with improved
performance, such as higher mobility, steeper subthreshold slope and lower VT [? ? ? ? ? ?
? ? ? ], circuit implementation is still somewhat constrained. This applies for most of the
material families including metal-oxides, organics, and amorphous silicon (a-Si:H) although
much less so with low temperature poly-silicon (LTPS). Here, a key design consideration is
the device-circuit interaction (DCI), which has to be accounted for when circuits are designed
with devices of poor performance and high degree of non-ideality [? ? ? ? ? ? ? ? ? ? ] as
compared to the CMOS counterpart. This is particularly true when the intrinsic performance
of TFTs does not the meet the requirements of a desired application. As shown in Fig. A.1,
if the performance of the desired application is much lower than the maximum achievable
intrinsic performance of the TFT, it is then possible to design the circuit independently
without considering device non-idealities. For example, when the error in the TFT’s output
current created by VT shift is much lower than the required accuracy, the VT shift problem
is not of concern. However, when the performance requirement needs to be higher than the
intrinsic performance, the designer should seek a compensation solution based on DCI or
wait for improvements in the technology. We will discuss the intrinsic performance of TFTs
in Section A.2 along with compensation methods in Section A.3.
Another aspect of DCI stems from the material and processing attributes of the TFT
which usually come with specific, and often self-limiting, properties. For example, in
analogue front-end and digital designs, alternative circuit architectures are needed to match
the properties of the CMOS counterpart [? ? ? ? ? ]. This will be discussed in Section A.4
along with solutions to deal with, for example, light-induced non-ideality in oxide TFTs.
100 Device Circuit Interaction
Fig. A.1 Illustration of DCI in relation to performance requirements of a desired application
A.2 Impact of TFT Properties
The TFT is the major building blocks of active thin film circuits and its properties determine
circuit performance. In applications such as displays and analogue front-end circuits, the
accuracy of the output signal strongly affects the quality of the displayed image without
mura (luminance non-uniformity) or in processing analogue signal without significant error.
The critical parameters for TFTs (e.g. mobility, Cox, VT , etc.) determine the performance
of the circuit and are more often discussed when comparing TFT behaviour or modelling a
single transistor’s terminal characteristics [? ? ? ? ? ? ? ? ]. However, other issues such as
stability, temperature sensitivity and process variations can also limit the overall performance
and may even affect the functionality of the circuit. There has been significant effort devoted
to the study and modelling of bias induced VT -shift [? ? ? ] and VT -shift compensation
in AMOLED pixel circuits [? ? ? ? ]. We will analyse the sensitivity of drain current on
VT -stability and temperature and process variations with the aim of establishing guidelines
on the level of accuracy that can be achieved without applying compensation methods (i.e.
the intrinsic performance) as well as identify the parameters that contribute most to error and
how this can be improved with processing.
A.2.1 Temperature Dependence
The parameters of the TFT are affected by material properties and on temperature, which in
turn impacts the terminal current-voltage (I-V) behaviour. According to the I-V model of the
A.2 Impact of TFT Properties 101
Fig. A.2 I-V characteristics of the examined TFT under different temperatures
TFT:
IDS ≈ 12+αp
µ∗0
Qαp−1re f
W
L′
Cαpox (VGS−VT )αp+1 ≡ K× (VGS−VT )αp+1 (A.1)
where,
K ≡ 1
2+αp
µ∗0
Qαpre f
W
L′
Cαpox (A.2)
The variations here can be specified as the variation of three key parameters: K, VT and
αp. By considering these parameters as functions of temperature, the derivative of IDS as a
function of temperature can be expressed as follows:
dIDS(T ) = (VGS−VT )αp+1∂K∂T dT
−K(αp+1)(VGS−VT )αp ∂VT∂T dT
+Kln(VGS−VT )(VGS−VT )αp+1∂αp∂T dT
(A.3)
Therefore the temperature sensitivity of the overall current can be separated into three
parts, in which each part of the function is determined by the temperature sensitivity of K,
VT or αp. The contribution of each parameter can then be calculated through extraction of
the temperature sensitivity of the three parameters.
102 Device Circuit Interaction
Consider the transfer characteristic for an indium-gallium-zinc-oxide (IGZO) TFT, mea-
sured every 10°C from 40°C to 80°C, shown in Fig. A.2. The results show that the overall
current would increase when temperature increases. To further investigate the degree of
influence of the three parameters, their values have been extracted from the measured transfer
characteristics according to Eq. (A.1). Here, we extract the threshold voltage (VT ) indepen-
dently from a multi-derivative method [? ], and then use it to calibrate the gate voltage as
VGS−VT . With this, I-V data is plotted in log-log plot. In this plot, all the data turns into a
linear behaviour, where the intercept on the y-axis, log(IDS), is log(K), with slope αp. From
this, we will get K and αp independently. The results are shown in Fig. A.3. As can be
seen, all three parameters are approximately linearly related to 1/kT in the temperature range
considered.
Therefore, through a linear fitting of the parameters, we get the empirical models of the
parameters with the following relations:
αp(T ) = α0+
Eα
kT
(A.4)
K(T ) = K0exp
(
−EK
kT
)
(A.5)
VT (T ) =VT0exp
(
−EV T
kT
)
(A.6)
Combining Eq. (A.4) (A.5) (A.6) and (A.3), the current sensitivity can be derived as:
dIDS(T )
dT
= (VGS−VT )αp+1K0 EKkT 2 exp
(
−EK
kT
)
−K(αp+1)(VGS−VT )αpVT0
EV T
kT 2
exp
(
−EV T
kT
)
−Kln(VGS−VT )(VGS−VT )αp+1 EαkT 2
(A.7)
Note that the three terms at the RHS of Eq. (A.7) define the contribution of K, VT and αp,
respectively.
To understand how much the overall current is affected by ambient temperature and the
associated contribution of the different parameters, the normalized temperature sensitivity is
shown in Fig. A.4. As can be seen, the overall temperature sensitivity drops with increase in
VGS due to the fact that the contribution of VT drops while VGS increases. This tendency starts
to saturate when VGS increases to 4V, when the contribution of K becomes dominant. This
analysis suggests that TFTs can be very unstable when biased at a voltage near VT . Although
higher stability can be achieved through intentionally biasing the transistor at higher voltage
A.2 Impact of TFT Properties 103
Fig. A.3 Extracted values of K, αp and VT at the different temperatures
104 Device Circuit Interaction
Fig. A.4 Normalized temperature sensitivity of current and the contribution of different
parameters at 313K
levels, the maximum achievable level will be determined by the temperature sensitivity of K.
As the temperature dependence of αp has a negative contribution to current with respect to
temperature and its contribution increases at higher bias, the temperature dependence of K
can be compensated by αp resulting in decreased sensitivity. However, a higher bias level
implies increased power consumption of the circuit. Therefore, an appropriate bias point
should be chosen for enough stability with acceptable power consumption.
A.2.2 Geometric Dependence
Apart from time- or temperature-dependent variations in device parameters, processing-
induced spatial variations should be considered especially in pixelated arrays or analogue
circuit applications. These variations would cause pixel non-uniformity in displays or
imagers and create error or undesired behaviour in analogue circuit design. Note that the
non-uniformity can be global (i.e. between panels) or local (i.e. between transistors). The
latter is harder to deal with especially when transistor matching is of concern (such as in
A.2 Impact of TFT Properties 105
differential pairs or current mirrors). This chapter will focus on the local non-uniformity and
discuss the contribution of different parameters in creating the current mismatch.
Analysis of geometric dependence can follow a similar route as with temperature depen-
dence. As different parameters would follow a certain probability distribution, the overall
current will be determined by the randomness of all three parameters according to Eq. (A.1).
As variations are usually smaller than the respective mean values, the mismatch in IDS can be
expressed as a first order approximation:
∆IDS = (VGS−VT 0)αp0+1∆K
−K0(αp0+1)(VGS−VT 0)αp0∆VT
+K0ln(VGS−VT 0)(VGS−VT 0)αp0+1∆αp
(A.8)
Here, K0, VT 0 and αp0 are the mean values of the parameters, and ∆K, ∆VT and ∆αp their
respective variations. Assuming K, αp and VT are independent variables and that all follow a
normal distribution, the variance of IDS can be expressed as:
σ2IDS = (VGS−VT 0)2(αp0+1)σ2K
+K20 (αp0+1)
2(VGS−VT 0)2αp0σ2VT
+K20 [ln(VGS−VT 0)]2(VGS−VT 0)2(αp0+1)σ2αp
(A.9)
where σK , σVT and σαp are the standard deviation of K, αp and VT , respectively. As expected,
the standard deviation of the overall current is determined by the deviation of all three
parameters.
To analyze the variation sensitivity of the overall current, we need statistical data for
all three parameters. Here, we acquired statistical data of the transfer characteristics by
measuring a 1080×1920 RGBW OLED display panel. By using the pixel circuit described
in [? ], which will be reviewed in the next section, we could extract the I-V characteristics of
the driver TFTs within the panel and extract statistical data for the three parameters. Here,
the TFTs for driving the green OLED pixels are used as shown in Fig. A.5. The probability
density functions are fitted to a normal distribution using MATLAB. With the fitted mean
values and standard deviations, we calculate the relative contributions of each parameter to
the current variance using Eq. (A.9).
The standard deviation of IDS and the contribution of each parameter are shown in
Fig. A.6. We see a similar overall curve in the sense that the sensitivity is higher when
biased near VT . However, unlike the temperature dependence where sensitivity drops with
increasing bias, the dependence on geometric shows a minimum at around VGS=6V. This is
due to the decreasing contribution of VT and the increasing contribution of αp. Therefore,
106 Device Circuit Interaction
(a) Fitted probability distribution and histogram of K
(b) Fitted probability distribution and histogram of VT
(c) Fitted probability distribution and histogram of αp
Fig. A.5 Fitted probability distribution and histogram of the three key parameters. The data
was extracted at room temperature from a 1080*1920 RGBW AMOLED panel with pixel
circuits as described in Fig. A.7.
A.3 Compensation Methods in Circuits & Applications 107
Fig. A.6 Normalized standard deviation of current and the contribution of different parame-
ters(K, VT and α)
analogue designers can intentionally choose a bias point close to the minimum point for the
output transistor, when designing circuits to reduce the output current sensitivity to process
variations.
The analysis of temperature and geometric dependence here is done using a generic
approach since the current-voltage behaviour is estimated by three key parameters, namely K,
VT and αp. This is adaptable to most TFT types because of the similar working principle albeit
with different parameter values. Therefore, the methodologies and derivations presented here
are generic and empirically approached for applicability to other material families including
OTFTs and related material families.
A.3 Compensation Methods in Circuits & Applications
.
The intrinsic performance of TFTs does not always meet the requirements of specific
applications. For example, the threshold voltage shift in TFTs creates visible shadows or
ghosting in displays or imagers after extended operation. The resulting non-uniformity
108 Device Circuit Interaction
creates mismatch in output characteristics especially in matrix architectures (displays or
sensors). These kinds of defects have proven difficult to improve by processing, and thus
need to be compensated through circuit solutions. Here, we will discuss VT shift and non-
uniformity compensation methods such as on-pixel programming and by off-pixel feedback.
The compensation methods can also be extended to other circuit applications.
A.3.1 On-Pixel Programming
The most common way of compensating TFT defects in active matrix arrays is through
on-pixel compensation. The methods were first developed for a-Si:H TFTs in AMOLEDs as
this family of TFTs have severe VT shift under positive bias, which leads to big errors when
supplying current to the OLED [? ].
VT compensation techniques can be categorized into two kinds: current programming [?
? ? ? ? ? ? ? ] and voltage programming [? ? ? ? ? ? ? ? ]. The basic working principles
of these have been reviewed in [? ? ]. Recent progress in voltage programming has been
reported in [? ? ]. Here, the working principle is slightly different from the original idea in
that the technique does not capture the cut-off point of a diode-connected transistor. Instead,
it uses a TFT to discharge a pre-charged capacitor with fixed gate bias in a fixed time period
to capture the TFT’s property (i.e. VT ). This technique can provide faster VT extraction and
is good particularly when the speed of the circuit is of concern.
A.3.2 Off-Pixel Feedback
Another way of defect compensation is based on off pixel feedback. Since in display
applications the driving period of each pixel can be separated into several phases, it is
possible to use part of the driving sequence to extract all of the defect and aging data present
in the pixel and then drive with revised extracted parameters as feedback [? ? ? ? ? ? ? ].
A pixel structure for defect extraction reported in [? ] is shown in Fig. A.7. The pixel
circuit shows a similar structure as the simple 2T1C structure – the only difference being
addition of a monitor line to monitor the TFT and OLED characteristics and extract their
defect and aging status. The driving sequence for this pixel circuit is similar to the 2T1C
except for the addition of a defect extraction phase. Defect extraction starts after the SEL
signal selects the pixel and before writing data to it. The extraction phase consists of two
parts – the driver TFT and the OLED, respectively (shown in Fig. A.8).
Fig. A.8a shows an equivalent circuit of the extraction phase for the OLED. In this phase
the gate voltage of the driver TFT is set to ground level to turn it off and the monitor line
is set to a higher voltage of VOLED. The current flowing through the OLED can then be
A.3 Compensation Methods in Circuits & Applications 109
Fig. A.7 AMOLED pixel structure for off-pixel defect extraction and feedback
captured by measuring the current flowing into the monitor line. As the I-V characteristic
of the OLED can be a signature of its efficiency, the aging of OLED can then be captured
from pre-acquired data for this type of OLED. In Fig. A.8b, the gate voltage of the driver
TFT is set to a higher level of VP. The TFT is then turned on and part of the drain current
flows to the monitor line. Combining the extracted I-V characteristic data of the OLED and
the voltage and current measurements in this phase, the I-V characteristic of the driver TFT
can be extracted.
After capturing the defect and aging data for both the driver TFT and OLED, the data
voltage for the desired luminance can be calculated and applied to the pixel by external
circuitry.
The aging and defect status of TFTs and OLEDs extracted through the monitor lines are
shown in Fig. A.9(a) and Fig. A.9(b), respectively. The sharp hazards that happen randomly
among the panel show the fabrication defects of the pixels. And the patterns in red, yellow
and green colour express the aging of each device. As the center of the displayed white
square has higher temperature due to self-heating of the surrounding pixels, the aging of
these pixels will be faster compared to other pixels.
The display panel using this method has the ability of compensating all kinds of defects
that can be extracted through the monitor line. The compensation results are shown in
Fig. A.10 depicting the defect status in Fig. 10(a)&(b) and temperature compensation in Fig.
10(c)&(d).
110 Device Circuit Interaction
(a) OLED detection phase
(b) TFT detection phase
Fig. A.8 Equivalent circuit for the defect extraction phase of OLED and TFT
A.3 Compensation Methods in Circuits & Applications 111
Fig. A.9 Extracted aging parameters for (a) TFTs and (b) OLEDs after continuously display-
ing a checker board (W: displayed with white squares, B: displayed with black squares)
Fig. A.10 Extracted aging parameters for (a) TFTs and (b) OLEDs after continuously
displaying a checker board (W: displayed with white squares, B: displayed with black
squares)
112 Device Circuit Interaction
This method provides a generic solution for TFT compensation and will be particularly
useful in compensation of mechanically-induced (reversible) defects or aging in flexible
displays. As measurement of the TFTs can be done in a monitoring phase, the obtained
parameters can then be used to bias the TFTs to have an ideal overall performance. The
geometric dependence of transistors can also be extracted from this pixel, as during the
sequence described in Fig. A.8a & A.8b one can also apply voltage sweep to obtain the
measured I-V characteristics for both TFT and OLED devices.
In summary, defects of TFTs can be compensated through separating the working se-
quence into several phases and by adding a compensation phase to extract and compensate
non-idealities. To apply this method to other analogue circuits, it is possible to intentionally
separate the working sequence and apply similar methods. Here, switch-capacitor circuits
can be a promising candidate. An example of this applied to analogue building blocks was
reported in [? ].
A.4 Specific Device Properties and Alternate Circuit Ar-
chitecture
Devices processed using different thin film technologies usually have a specific property,
which can sometimes be self-limiting. This requires the use of alternate circuit architectures.
For example, most TFT technologies lack complementarity, thus the circuits have to be
designed using mono-type devices, which means the designs cannot benefit from the well-
established CMOS architectures. Specifically, the load of an analogue amplifier needs to
be redesigned to achieve high gain as the complementary load is not applicable. Another
example is persistence photoconductivity in oxide TFTs, which, while ideal for image capture,
requires a sharp gate a pulse to reset for high frame rates. We will discuss these examples in
the following.
A.4.1 Analogue Gain Stage with Mono-type TFTs
CMOS gain stages benefit from the complementary structure [? ? ? ]. For example, in the
case of NMOS as the input stage and PMOS as the load, the gain of the stage can be boost up
to the order of magnitude of gmro. The use of PMOS load provides large enough bias current
with small voltage and, at the same time, big small signal resistance. These requirements are
hard to be achieved with only one type of transistors.
To simplify the problem, we consider a single common source amplifier stage as shown
in Fig. A.11(a). Here, the load is considered as a two terminal device. Assuming the bias
A.4 Specific Device Properties and Alternate Circuit Architecture 113
Fig. A.11 (a) Common-source gain stage of an amplifier (b) sketch of different type of loads
passing through the same bias point
conditions of the driver TFT is fixed (to maintain gm for fair comparison between different
loads), the load of this gain stage would have fixed bias current. Here, we consider a fixed
bias point of the load for comparison, i.e. the I-V characteristic of the load should pass a
fixed point in the I-V plot (Fig. A.11(b)). As the gain stage needs a higher small signal
resistance of the load to produce high gain (i.e. derivative at the bias point should be close to
zero), the current is better a concave function of voltage which means p-type load is more
beneficial. Note that for other type of loads, the same small signal resistance can only be
achieved by moving the bias point to the right hand side, i.e. increase the voltage bias of
the load. However, a higher voltage bias would yield higher power consumption. From
this standpoint, we conclude that for high gain, a p-type load with fixed gate bias (concave
function) is more beneficial than a resistive load (linear function) and, subsequently, a diode
or diode-connected TFT load (convex function) as it yields higher gain at the same power
consumption.
The most familiar concave function in TFT behaviours is the output characteristic (ID−
VDS characteristic with fixed VGS). However, the design is limited by the connection of n-type
devices as the source terminal of the load TFT is connected to the output node of the gain
stage. Thus, the gate terminal of the TFT cannot be chosen as a fixed level but should follow
the change of the source terminal.
114 Device Circuit Interaction
Fig. A.12 Gain stage of an amplifier with (a) feedback load (b) boost strap load
One straight forward solution is to use a depletion mode load and short circuit the load
transistor’s source and gate terminals. (Depletion mode transistor can work in saturation
regime with zero VGS.) Amplifiers have been designed around 1980s to achieve high gain
with depletion and enhancement NMOS transistors [? ? ? ]. However, in TFT circuit
area, this approach is limited by process complexity. By far, only digital circuits have been
fabricated out of depletion load [? ? ? ].
In order to use only enhancement mode TFTs while still obtaining high enough gain, it is
also possible to use feedback loop to maintain a fixed VGS for high small signal resistance of
the load. One approach is reported in [? ? ]. The circuit reported is shown in Fig. A.12(a).
Here, an analogue adder is designed for the DC bias of the load transistor. The feedback
circuit, in effect, adds a bias voltage to the source terminal of the load transistor and applies
the resulting voltage to the gate terminal. Here, the feedback voltage at the gate terminal of
the load TFT can be calculated as:
VF =VH −VB+VO (A.10)
Here, VH and VB are external bias voltages and VO is the output of the gain stage (which
is also the source terminal voltage of load). As the feedback voltage contains the output, this
topology has a positive feedback.
Another approach using positive feedback has been reported by H.Marien et al [? ]. The
load of their gain stage is designed with boost strap structure. Other than maintaining the
A.4 Specific Device Properties and Alternate Circuit Architecture 115
VGS level of the load TFT, the structure successfully separates the DC bias and the small
signal resistance and as a result obtains a higher gain for small signals at a higher frequency.
The circuit needs a large capacitor for the load (a high pass filter) to reduce its lower 3dB
frequency close to DC range. This also makes the circuit hard to work at very low frequencies,
especially when the original signal is close to DC. An NMOS version of the circuit has been
shown in Fig. A.12(b). Other approaches regarding positive feedback are also reported in [?
].
To summarize, positive feedback is used for gain-enhancement in single type TFT
amplifiers. The major problem of this kind of approach is that positive feedback sacrifices
the phase margin (PM) of the amplifier and would potentially cause instability. Although
a cascode technique can be chosen to enhance the gain without sacrificing PM, it is not
preferred in TFTs since a much higher supply voltage is needed because of the high threshold
voltage of TFTs.
A.4.2 Persistent Photoconductivity
This can arise depending on the channel composition in oxide transistors when the transistor
is under exposure to ambient light or when subject to negative bias illumination stress (NBIS)
[? ][21]. As the drain current of the TFT increases after exposure to ambient light, it is
possible to use this characteristic for photo-sensing applications. In this application, the
variation of current is not a defect that needs to be compensated. However, to use this
property, the slow recovery process makes it hard to capture the changing image at high
frame rate or to restore the TFT’s initial state. Fig. A.13(a) depicts the drain current of
an IGZO TFT under periodic luminance and darkness. The results show the drain current
recovering only slowly even in a completely dark environment.
In order to remove the persistent photoconductivity and recover the TFT to its original
state, it has been found that by applying a positive pulse to the gate of the TFT, the PPC
can be eliminated very quickly. The results in Fig. A.13(b) show that fast PPC removal is
possible after the gate pulse technique.
The phenomenon of PPC is explained by the band diagram shown in Fig. A.14. As the
ambient light excites the electrons in defect states to the conduction band, ionized oxygen
defects are created. The excited electrons effectively increase the conductivity of the device
as the electron concentration is increased. In order to accelerate the recovery process, the
recombination of photo-induced electrons and ionized oxygen defects VO2+ needs to be
accelerated. By applying a positive voltage pulse to the gate of the transistor, the electrons
are swept away from the conduction band to recombine with the ionized oxygen defects thus
removing the PPC.
116 Device Circuit Interaction
Fig. A.13 Band diagram to explain the effect of positive gate pulse on recovery.
PPC removal is a great example of device circuit interaction as the defect (i.e. light
induced instability) of a TFT can actually be utilized to sense luminance signal, i.e. as a
photo sensor. Indeed DCI should be considered not only to enhance circuit performance
and/or overcome difficulties in the design but also to utilize specific properties stemming
from the operating environment.
A.5 Conclusion
This chapter reviewed and analysed the intrinsic parameters of TFTs and proposed ways
of analysing the maximum achievable current accuracy of TFTs and to help determine
when compensation becomes mandatory to enhance reliability and combat ageing. We
presented techniques for extraction of defects and aging in devices using closed-loop feedback
techniques and discussed their extension to other applications. In summary, device circuit
interactions are crucial when designing high performance circuits and systems to either
utilize or minimize the impact of intrinsic adversaties associated with low temperature thin
film technology. Consideration of device circuit interactions in design of TFT systems
is even more compelling than the case of CMOS technology because of the wide range
of materials imperfections, which give rise to device instability and large area processing-
induced non-uniformity. Of specific importance to mechanically flexible systems is the impact
of bending-induced (reversible) defects and associated aging, which makes compensation
A.5 Conclusion 117
(a) Observation of persistent photoconductivity (PPC) as a slow recovery
(b) Removal of PPC with a positive gate pulse to get fast recovery
Fig. A.14 Persistent photoconductivity (PPC) and its removal
118 Device Circuit Interaction
even more compelling. The techniques presented here can extend the current application of
TFTs from active matrix pixelated arrays to newly-emerging application area that require
TFT operation in analogue operation mode.
Appendix B
Subthreshold Operation for Schottky
Barrier TFTs
B.1 Introduction
Recent research has shown that by biasing IGZO TFTs in deep subthreshold region could
improve the small signal gain and significantly reduce the power consumption [? ]. This is
specifically useful in low power applications such as sensor networks, bio-medical sensing
etc [? ? ].
While subthreshold operation in Silicon based CMOS devices had been intensively
researched in 1970s with great success in Swiss watch industry [? ? ? ? ], the same has not
been done for TFTs.
Due to the low effective carrier mobility of TFTs (perhaps with polysilicon as an ex-
ception), TFT devices are generally working in a lower current level [? ? ]. Although this
could limit the speed of the device, TFTs can be naturally suitable for low speed and low
power applications. Biasing TFTs in subthreshold region could further reduce the power
consumption to sub-nano-watt. This is particularly appealing as battery-less operation could
be possible with this level of power consumption. However, as the subthreshold region is
generally very narrow and current level is very sensitive to bias [? ]. If a TFT has a steeper
subthreshold slope (SS), a sensitivity of current variation is higher. The circuit design for this
kind of devices could be challenging although a steep SS provides a high intrinsic gain. Here,
a high intrinsic gain is an important property for circuit design, so many approaches to get
it have been introduced for the above-threshold operation [? ? ? ? ]. For the subthreshold
operation, it is known than a TFT with a Schottky contact source/drain have a steeper SS
120 Subthreshold Operation for Schottky Barrier TFTs
compared to an Ohmic contact TFT [? ? ? ], thus a Schottky contact TFT provides a higher
intrinsic gain within the subthreshold regime with a difficulty in a circuit design.
In this chapter, we will analyze several figures of merit for deep-subthreshold operating
TFTs in analog circuit design with the aim of providing a guideline of analog circuits design
capability of TFT devices using general architectures.
B.2 Subthreshold Model for IGZO TFTs
B.2.1 DC Model
The transfer curve of SB-TFTs in deep-subthreshold is reported to be linear in log-scale
which is similar to CMOS devices. Here we convert the model reported in [? ] to a more
macroscopic form to help analyze the performance. The equation for drain voltage (VDS) >
saturation voltage (vsat) is derived as follows [? ? ]:
Ids = I′0 exp
(
VGS−VT
SS/ ln10
)(
1+
VDS
VA
)
(B.1)
where I′0 is the effective subthreshold reference current at VT normalized by W and SS is the
subthreshold slope. VT is the threshold voltage and VA is the effective early voltage. The
effective values can be derived as
I′0 ≡ AJJ0 exp
(
VT −Vre f
SS/ ln10
)
(B.2)
where J0 is the reference current density at Vre f , AJ is the junction area of the Schottky
contact at the source and drain. In a Schottky contact TFT, AJ is proportional to the channel
width (W) [? ].
VA ≡ n · vth exp
(
vsat
nvth
)
(B.3)
where n is the ideality factor of the junction and vth is the thermal voltage.
With the above equations we can easily connect the DC parameters to several important
small signal parameters such as gm and ro.
B.2.2 Small Signal Model
Although in previous publications [17], [18] we analysed the small signal mode for TFTs
and figured out that contact resistance can cause big errors using CMOS small signal models,
B.3 Figures of Merit 121
small signal behaviour in subthreshold region can still be correctly modelled by CMOS
model. This is due to the fact that channel capacitance in subthreshold is very small and
normally negligible compared with overlap capacitance in TFTs.
Here we consider Cgs and Cgd are mainly the overlap capacitance at source and drain side
[17]. The tranconductance and output resistance can be calculated as:
gm = ln10SS I
′
0 exp
(
VGS−VT
SS/ ln10
)(
1+ VDSVA
)
= ln10SS IDS
(B.4)
ro =
IDS
VA
(B.5)
These equations take exactly the same form as the CMOS counterpart.
B.3 Figures of Merit
In this section, we consider several figure of merit for TFTs with emphasize in the subthresh-
old region. The model used for the simulation is based on the [? ] and parameter values are
extracted using the same samples. The W/L of the TFT under test is 50µm/20µm.
B.3.1 Intrinsic Gain
Intrinsic gain is an important figure of merit for analog amplifier as it reflects the highest
achievable single stage gain for an amplifier. The simulation based on the model developed
earlier is shown in Fig. B.1. As seen, the intrinsic gain in subthreshold region is related with
subthreshold slope and the ideality factor n of the Schottky junction.
The expression of the intrinsic gain can be approximated as:
Ai = gmro =
ln10
VA ·SS (B.6)
This suggests that intrinsic gain is reverse proportional to the SS of the TFT. By pushing the
SS to its theoretical limit (60mV), one could get over 1000 intrinsic gain with even less ideal
Schottky-Barrier at source-semiconductor contact (smaller n). The expression also suggests
that the value of intrinsic gain is rather independent on the bias of the transistor as long as it
is working in subthreshold region.
Ideality factor n contributes to the intrinsic gain of the transistor because it controls the
effective Early voltage (VA) and thus influence the output resistance of the TFT.
122 Subthreshold Operation for Schottky Barrier TFTs
Fig. B.1 Simulation result for the intrinsic gain (Ai) of the Schottky-Barrier IGZO TFT
(SB-TFT). The parameter n is the ideality factor of the source-semiconductor junction.
B.3.2 Transconductance Efficiency
Transconductance efficiency (gm/IDS) is another important figure of merit for electron devices.
It represents the efficiency of converting the bias current into an equivalent transconductance.
For analogue TFT circuits, as the voltage bias is normally limited by the driving circuitry and
the application, reducing the current bias while maintaining a high gm also means reducing
the power consumption while keeping the circuit performance.
As can be seen from Fig. B.2, the highest gm/IDS can be obtained only at deep- sub-
threshold region for a TFT before it enters a transition region to above-threshold. This
value remains a constant at deep-subthreshold due to the exponential nature of the TFT
subthreshold behaviour. The simulation result also suggests that this value would increase if
the TFT has a steeper subthreshold slope.
The expression of the gm/IDS value can be estimated as:
gm
IDS
=
ln10
SS
(B.7)
For above-threshold region, the gm/IDS value drops as the TFT enters above-threshold
region, where the expression is:
B.3 Figures of Merit 123
Fig. B.2 gm/IDS from deep subthreshold to above threshold region. The value reaches
maximum at deep subthreshold and increases with steeper SS.
gm
IDS
=
2+α
VGS−VT (B.8)
where α is the coefficient on the power law of TFT model, α=0 for the case of MOSFET
[17]–[19]. Therefore, biasing a TFT at a high gate voltage would result in a less efficient gm
conversion and thus higher power consumption.
B.3.3 Cut-off frequency
Cut-off frequency ( fT ) is also considered as the current gain bandwidth product as the current
gain at fT is equal to 1 [17]. This value will limit the actual gain bandwidth product of
amplifiers designed by the device. The simulation result of fT is shown in Fig. B.3. Here fT
is small as the overlap capacitance of the TFT under test is quite big. The overlap length here
is 50µm, which is even bigger than the channel length of the device. Practically, this value
can be reduced to a few µm or even lower with self-aligned process.
124 Subthreshold Operation for Schottky Barrier TFTs
Fig. B.3 Cut-off frequency vs. voltage bias for different SS.
Fig. B.3 suggests that this product rolls off pretty quickly in subthreshold region. The
expression of fT can be derived as follows:
fT =
gm
2πCov
=
IDS · ln10
SS ·2πCov (B.9)
The expression shows that the value of fT is proportional to IDS, thus the quick roll of at
subthreshold is explained by the current roll off in subthreshold region. As IDS and Cov are
both proportional to the channel width of the TFT, fT would be independent of channel width.
In addition, by reducing the overlap length, one could further reduce the overlap capacitance
(Cov) to increase the frequency response.
The expression also suggests that biasing the TFT in a deeper subthreshold region would
at the same time pushing the frequency response lower proportionally. Therefore, it’s
maybe desirable to have a less steep subthreshold slope in terms of speed when considering
subthreshold operation.
B.4 Sensitivity to Variations and Bias 125
Fig. B.4 Normalized sensitivity to VT shift for different SS
B.4 Sensitivity to Variations and Bias
B.4.1 Current Sensitivity to Variations
Here, we assume the threshold voltage shift is also a uniform shift in subthreshold. A
non-uniform shift in subthreshold would mean a change in subthreshold slope, which will be
discussed later. Therefore, the VT shift at abovethreshold is the same as a reference voltage
shift at subthreshold. As the reference voltage shift is equivalent to a bias voltage shift. This
curve can also be used for testing the sensitivity of bias voltage inaccuracy.
Fig. B.4 shows that at deep subthreshold region the normalized current sensitivity to VT
shift is a constant. The sensitivity becomes lower when the TFT is approaching and enters
above threshold region. As VT shift is equivalent to bias shift, the sensitivity expression can
be the same as the gm/IDS curve (as gm = dIDS/dVGS is also a sensitivity to bias) just with an
opposite sign. For deep-subthreshold:
dIDS
dVGS
/IDS =− ln10SS (B.10)
For above-threshold:
dIDS
dVGS
/IDS =− 2+αVGS−VT (B.11)
126 Subthreshold Operation for Schottky Barrier TFTs
Fig. B.5 Normalized sensitivity to SS variations for different SS mean values
Now we assume the change in SS would not affect VT of the above threshold region.
Therefore, the subthreshold current of different SS would meet at around VT . This yields the
results shown in Fig. B.5, where the normalized current sensitivity would drop when the TFT
is biased closer to VT . In above threshold region, the parameter SS do not contribute to the
equation of IDS. The sensitivity is therefore zero. The curve also shows that a steeper SS
would increase the current sensitivity.
The expression for the current sensitivity in subthreshold is shown below:
dIDS
dSS
/IDS =−(VGS−VT ) · ln10SS2 (B.12)
The above equation suggests that the sensitivity is reverse proportional to SS2. Therefore,
a steeper SS would yield a high current sensitivity on the variations of SS. In summary,
although steeper SS would give rise to gm/IDS and potentially further reduce the power
consumption, the sensitivity on process variations of SS and VT would increase, possibly
narrowing the design window for analog circuits.
B.4 Sensitivity to Variations and Bias 127
Fig. B.6 The useful bias range for a depletion load common-source amplifier. (a) conceptual
figure of the load line and transfer curve of the amplifier, where green curve illustrates the
correct bias condition and blue curves illustrates that the amplifying TFT is biased out of
useful bias range (b) circuit schematic of the amplifier (c) simulated useful bias range with
respect to SS
B.4.2 Accuracy Requirement for Biasing Circuitry
Here, we take a common source amplifier with depletion load as example (Fig. B.6(b)). The
load line and bias conditions is shown in Fig. B.6(a). As can be seen, bias conditions should
keep both transistors working in saturated region, i.e. the VGS for the green line in Fig. B.6(a).
The blue lines show either of the two TFTs is working in a not saturated region.
Therefore, to maintain a high gain, VDS for both TFTs should follow VDS > vsat . As the
value of vsat for different VGS stays the same in subthreshold, the input voltage range can be
calculated as:
Vrange =
2 ·SS (VDD−2vsat)
VA ln10
(B.13)
128 Subthreshold Operation for Schottky Barrier TFTs
B.5 Conclusion
We investigate several figures of merit of TFT’s subthreshold operation including Ai, gm/IDS,
fT and the design sensitivity for biasing circuitry and device variations. The results of this
chapter could benefit researchers working in device fabrication and circuit design while
considering subthreshold operating TFTs specifically from a device performance perspective
to a lower level analogue design. The results suggest that one could get high Ai, gm/IDS
through biasing TFTs in subthreshold region at the cost of reduced fT and increased sensitivity
to bias and process variations. Another interesting conclusion is that TFTs with less steep
subthreshold slope can still benefit from a high Ai and gm/IDS, but with reduced sensitivity
to variations and less strict requirement on accuracy of biasing circuitry.