Toward Single-Cell Multiple-Strategy Processing Shift Register Powered by Phase-Change Memory Materials

programmable shift register con ﬁ guration is demonstrated with a serial-in – serial-out processing strategy, as well as more complex repro-grammable processing schemes using the M state-type platform, showing previously unreported nonvolatile shift register types with multiple processing approaches. This paves the way for development of next-generation low-power-electronic systems using two-terminal-based semiconductor materials

Modern innovations are built on the foundation of computers. Compared to von Neumann architectures having separate storage and processing units, inmemory operation utilizes the same primary structure for data storage and register operations, therefore promising to decrease the energy cost of computing in data centers significantly. While various studies centered on exploring novel device architectures, designing suitable material platforms is extremely challenging. Herein, all four material (M) states of a phase-change material (PCM) in data storage and register operations are utilized and a combined M state-based model framework for developing in-memory operation is demonstrated, along with nonvolatile, reprogrammable single-cell shift register operations. A previously unachieved multiple-level-per-volt different-initial-state multilevel set process with further computing in the M state-based platform is realized. The simplest case of a programmable shift register configuration is demonstrated with a serial-in-serial-out processing strategy, as well as more complex reprogrammable processing schemes using the M state-type platform, showing previously unreported nonvolatile shift register types with multiple processing approaches. This paves the way for development of next-generation low-powerelectronic systems using two-terminal-based semiconductor materials.
In archetypal computer memory hierarchy, the memory technologies are grouped into three groups depending on their storage capacities and access times ( Figure 1). [17] For conventional high-speed/cache memory technologies, the devices have short access times but small storage capacities. [18] For traditional main memory technologies, the storage capacities and access times are moderate. [19] For conventional storage technologies, the storage capacity is large but the access time is long. [20] Considering the large time gap between the typical main memory technology and archetypal storage technology, as well as between the conventional high-speed/cache memory technologies and archetypal main memory technology, a new in-nonvolatile-memory register technology, using the same basic device structure for fast register operations and nonvolatile data storage, is presenting itself as an ideal hardware technology for bridging the gaps between these memory platforms. This could open the path to substantially reduce the time needed to shuffle data not only between the prototypical main memory (DRAM) and typical storage (flash), but also between the conventional high-speed/cache memory (register/SRAM) and traditional main memory (DRAM), which has not been presented before. Moreover, this would allow us to achieve lower energy consumption and further enhance device miniaturization, tackling portable data-intensive and adaptive register applications. The success of this approach depends on identifying an ideal material system capable of harnessing the full potential of this architecture.
Two-terminal-based memristive materials can combine advantages for realizing next-generation shift register and memory. Experiments have demonstrated shift register/logic configurations using magnetic-based materials, [21,22] as well as resistive switching materials. [23,24] However, traditional two-terminalbased memristive materials can have low functionality, [25] which limits the number of shift register operations. Moreover, avoiding the loss of locally stored information when power is turned off and high cell count for processing each bit in traditional charged-based shift registers [26] remain crucial to realizing low energy and compact systems.
Phase-change materials (PCMs) are promising candidates for next-generation digital memories and shift registers. Phasechange (PC) cell operations, based on reversible switching between the amorphous state and crystalline state of a chalcogenide alloy, showing marked contrast in electrical conductivity and optical reflectivity, are generally fast on several ten nanosecond timescales. [27] Recently, some PCMs have made inroads into nanophotonics whereby picosecond switching at multiple states has been demonstrated. [28,29] Moreover, experiments have shown that the energy consumption and crystallization time of PCMs can be reduced by utilizing multilayered thin films and nanostructures, respectively. [30,31] Additionally, chalcogenide materials exhibiting crystallization in GST/AIST layers, as well phase separation/grain growth in the Ge-Ga-Sb layer were demonstrated in recent studies. [32][33][34] Different degrees of crystallization, phase separation/grain growth in the active layer were disclosed. The conventional material states associated with the set and reset operations in PC memory devices involve two states: the fully crystalline and amorphous PCM states. Additionally, it has been demonstrated that priming of the amorphous state, which is termed as a "primed" state, can result in fast set operations. [35] Although negligible difference exists in the electrical resistance, the primed state is distinguished from the amorphous state in terms of their distinct responses to electric or thermal stimuli. [36,37] Furthermore, partially crystallized states have been utilized for neuromorphic applications, in which multilevel set processes were enabled. [38] Herein, we demonstrate that by stimulating and utilizing all four material states (we call them M states) of PCMs in data storage and register operations, we can achieve a combined M state-based configuration framework for in-memory operation, as well as reprogrammable, nonvolatile single-cell shift register operations. This new approach enables a previously unachieved multiple-level-per-volt different-initial-state multilevel-set process with further computing using a M state-based platform, rather than the traditional single-level-per-volt-only sameinitial-state pure multilevel-set process. We demonstrate the simplest case of a programmable shift register model with a serial-in-serial-out processing scheme through M state-based framework. We then show that this concept can be extended to implement reconfigurable shift register modes with a more complex processing strategy (serial-in-parallel-out) in the M state-based platform, disclosing previously unreported nonvolatile shift register varieties with multiple processing approaches. We further demonstrate short crystallization pulses, together with low resetting energies. These pave the way to achieve faster and energy-efficient digital computer operations.

Results and Discussion
To demonstrate how we can achieve shift register configurations that have not been shown before, it would be instructive to discuss the theoretical aspect of crystallization kinetics, which involve all M states of PCMs, i.e., not only the conventional www.advancedsciencenews.com www.advintellsyst.com amorphous and fully crystallized states, but also the primed state and partially crystallized states. We first demonstrate the relationships between the four states induced by different thermal histories. Figure 2a shows the possible variation of the amorphous state of PCMs induced by the application of a stimulus pulse. Two different stimuli, each having a different amplitude, were utilized. Each stimulus could result in a different resistance corresponding to the high/intermediate resistance state, which are grouped into the region I or II in the resistance-voltage diagram in Figure 2a. [39,40] In region I, the stimulus generates primed states. In region II, partially crystallized states are created. After injecting a subsequent bias pulse to each of the M states (Figure 2b), the final state shows a smaller value of resistance (R state 2 ) (or equivalently, an enhanced crystallinity), whose relative values depend on the resistance of initial M state (R state 1 ). The stronger is the stimulus, the smaller the final The stimulus is applied to the cell to achieve the resistance of state 1, R state 1 , followed by the subsequent pulse to change the resistance of the cell from the R state 1 to the resistance of state 2, R state 2 . The error bars exhibit the range of values obtained from experiments carried out on three different cells. The details of the statistics can be found in the section Statistical Analysis. c,d) Schematic description of the evolution of cluster-size distribution models upon stimuli corresponding to different regions c) I and d) II in the R-V diagram and subsequent bias pulses. n am and n p (t) denote the cluster-size distributions of the amorphous state and primed state, respectively. The n pc,i (t), n pc,ii (t), and n pc,iii (t) describe the cluster-size distributions of partially crystallized states. Finally, n c,ss represents the cluster-size distribution of the fully crystalline state. e,f ) Schematic illustration of the phase-change cell after injecting stimuli corresponding to different regions e) I and f ) II in the R-V diagram and subsequent bias pulses. g) Peak temperature variation for crystallization of phase-change cells with different electrical resistivities and bias voltages. h,i) Thermal distributions of the cells with h) large resistivity and i) small resistivity after injection of subsequent bias pulses.
www.advancedsciencenews.com www.advintellsyst.com resistance/R state 2 becomes (Figure 2b). If we focus on the change in the resistance accompanied by an amorphous-to-crystalline transition, when the M state is generated by a stronger stimulus, the application of a subsequent bias pulse to the M state results in a final state that shows a smaller change in resistance (i.e., a smaller change in the degree of crystallinity). Each of the M states described above may be represented by their own cluster-size distributions that form the basis of kinetic theory of nucleation. [33,36] According to this theory, the decrease in the final resistance after the subsequent bias pulse upon a stimulus can be described by its history of cluster-size redistribution. In the cases of the primed state [40] or partially crystallized states, [41] they can be described by their enhanced degree of medium-range order or crystallization, respectively, compared to the disordered network structure of the amorphous state that fluctuates locally after excitations. From the point of view of the kinetic theory of nucleation, this corresponds to the case that, in response to a temperature change, the cluster population of the melt-quenched amorphous state n am (the blue lines in Figure 2c,d) evolves gradually to the steady-state cluster-size distribution for the primed state n p (t) (the green line in Figure 2c), to the one for partially crystallized states n pc,i (t), n pc,ii (t), and n pc,iii (t) (the green lines in Figure 2c,d), and finally to n c,ss (for the fully crystallized state) at an increased temperature. [36] This temperature dependence is a consequence of the thermally activated process during the growth of clusters, which involves atomic attachment or detachment via thermal fluctuations. [36] The kinetic theory of crystallization thus indicates that, by controlling the strength of the stimulus proposed in this study, one could, in principle, achieve a selective phase transition of the amorphous state to either the primed state (generated by priming pulses with weak pulse amplitudes) or partially crystallized states (bias pulses with weak-moderate pulse amplitudes are utilized). A subsequent application of the bias pulse (i.e., a pulse for complete crystallization) can induce a transition to the fully crystallized state (created via set pulses with moderate pulse amplitudes). A much stronger reset pulse can then transform all these states to the initial amorphous states (reset pulses with strong pulse amplitudes are used). Hence, all these four states of PCMs can be realized by the delicate control of priming, bias, set, and reset pulses. The electrothermal simulations of the thermal distribution in PC cells (Figure 2g-i, S1, Supporting Information) disclose the basic origin of the different degree of Joule heating responsible for the different degree of thermal excitation (and thus structural ordering or disordering) induced by these pulses.
We now demonstrate how we can modulate the degree of order/disorder in M states based on the above strategy.  Figure 3a. A similar behavior is also observed for the final resistance of the pristine cell (the final resistance of the cell with an initial high resistance level that is described by R final, HI ). Moreover, we investigated the absolute percentage change in resistance where R initial is the resistance of the initial state and R final is the resistance of the final state. The ΔR % increases with increasing bias voltages (from 0.5 to 0.8 V) (Figure 3b). Besides, the ΔR % for the low-resistance M state, obtained with a stimulus amplitude between V c and V set , is small after injecting the subsequent bias voltage between 0.5 and 1 V, which indicates that the degree of crystallization is small. On the other hand, when the resistance of the M state is high (obtained with a stimulus amplitude below V c ), the ΔR % is large for subsequent bias voltages between 0.5 and 1 V, indicating that a large degree of crystallization can be achieved. Thus, variations in the crystallinity can be controlled by varying the M state under the application of same subsequent bias voltage. Moreover, the contrast in the final resistance obtained for different M states is small after injecting subsequent bias voltages between 0.8 and 1 V, which shows that when the absolute value of the measured final resistance is utilized as a measure of contrast, the fully crystalline states obtained for different M states can be undifferentiable. On the other hand, the contrast in the ΔR % obtained for different M states becomes more noticeable after injecting the subsequent bias voltage between 0.8 and 1 V, indicating that the fully crystallized states obtained for different M states are now more differentiable compared to the case when absolute final resistance values are utilized. As a result, the differentiability of the fully crystalline states obtained for different M states can be substantially enhanced by choosing an appropriate analytical methodology. Up to this point, a conventional PCM (GST) has been utilized to provide excellent stability of the M state. We developed a method by which we can alter the M state for enhancing PCM performance by utilizing a more stable active layer, without using pure GST. This requires increasing the stability of the amorphous state using a doped PCM (GST doped with nitrogen). Experiments have demonstrated that incorporating nitrogen into the PCM is an efficient way to improve the data retention/stability of amorphous states by hindering crystallization. [42] A similar type of material was utilized in this work, which indicates that our strategies are similar. After setting the initial state of the cell to the amorphous state, a specified M state is created in the doped active layer using a stimulus ( Figure S3, Supporting Information). The same operation (Figure 3a) using different M states, obtained with different stimulus amplitudes between 0 and V set , generates different degrees of crystallization in the doped active layer after injecting subsequent bias voltages between 0 and 0.9 V. Each of these M state control operations results in stepwise changes in the final resistance. Figure 3c,d shows the final resistance and ΔR % as a function of material types. Notably, the ΔR % becomes smaller with a change in the active layer from the GST to doped GST, which shows that the degree of crystallization can be modulated by varying the PCM type. We next show that a substantial degree of crystallization/ change in the M state can be achieved with two pulses injected at the same time/a combined strong pulse injected in the doped PC layer. The active layer was initially switched to the amorphous state. We applied a weak/moderate subsequent bias pulse, which would result in a small degree of crystallization. Moreover, to achieve a large degree of crystallization, a combined strong subsequent bias pulse was administered. The amplitude of the strong bias pulse was set to be the sum of the amplitudes of the weak and moderate bias pulses. The expected degree of crystallization was consistent with the obtained variation in the final resistance and ΔR % (Figure 3e,f ). The ΔR % increased with a change in the bias pulse type from a pulse to two pulses/a combined strong pulse.
However, when a large degree of crystallization, which can be identified from the resistance of the M state, was created in the active PC layer, the subsequent resistance modulation operation with crystallization pulses has no substantial effect. In this case, the degree of crystallization in the active layer remains almost unchanged, and its crystalline state can only be altered after applying a strong reset pulse (larger than amorphization voltage) with a short pulse length. The amorphization voltage decreases www.advancedsciencenews.com www.advintellsyst.com as the active layer is changed from GST to doped GST ( Figure S4, Supporting Information). These indicate that annihilation of the crystallized state is facilitated with a doped active layer. Moreover, when a switching from the low resistance state to high resistance state is considered, the energy required for this process to occur would be large due to the high resetting current required for PC cells. In this example, the largest resetting energy utilized for the doped GST cells is 2.0 V Â 1.7 ns Â 0.6 mA ¼ 2.0 pJ ( Figure S4, Supporting Information); thus, a small reset energy was achieved.
Using the concept of variable M states demonstrated above, we realized the creation of a shift register configuration, namely, a three-bit shift register model with a serial-in-serial-out processing scheme in which the binary data is coded as the degree of crystallization/amorphization of the PC cell, whereby a single value of the cell resistance represents a type of the three bit data written ( Figure S5, Supporting Information). Experiments have demonstrated the utilization of a conventional shift/write/read protocol to achieve nonvolatile shift register types [43][44][45] ( Figure S7, Supporting Information). Based on this protocol, we generated the M state-based shift register modes ( Figure S5, Supporting Information). Moreover, to demonstrate the state of the cell for each bit and correct positioning of the output bit, a modified protocol (write/shift/read) was utilized ( Figure S8, Supporting Information). The modified protocol with an initialization process (initialize/write/shift/read) was further used to achieve an increased resistance window (Figure 4, 5 and S10-S12, S14-S16, Supporting Information). Utilizing the initialization-based modified protocol, the data were written into the cell in the active layer, were shifted by five sets of crystallization/amorphization pulses, and then retrieved from the final state of the active layer ( Figure 4). The change in the degree of crystallinity with the applied pulses was inferred from ΔR % . For encoding binary data "0" or "1" from the ΔR % , we defined the reference value of the ΔR % as ΔR %, ref . The final encoded binary data were then defined as "0," when the output resistance change (ΔR %, out ) is smaller than ΔR %, ref , and as "1" when the ΔR %, out is larger than ΔR %, ref ; therefore, a small change in the resistance with respect to ΔR %, ref represents a "0," and the large change in the resistance with respect to ΔR %, ref indicates "1." In majority of the cases, a transition between two different resistance regions (regions I, II, or III, as defined in Figure 2a) leads to the output "1," while the output "0" results for the case when the initial and final resistances remain in the same region. As a result, it can be considered qualitatively that a large degree of crystallization/amorphization leads to "1," and "0" results for the case when the degree of crystallization/amorphization is small. For example, when a data sequence "100" is written in the cell, the ΔR % and the corresponding cell configuration evolved (Figure 4b,c). In Figure 4d, the colored numbers correspond to write/shift operations. The input sequence is transferred to the output after five write/shift processes. In this example, the longest operating time to write/ shift a bit is %12 ns, which was determined by the crystallization pulse length utilized for representing an input low (LO). A low constant priming bias was also used to facilitate the crystallization operation. In this case, the crystallization pulse length decreases from 12 to 1.9 ns with an increase in the priming bias from 0 to 0.35 V (Figure 4e), so that a maximum write/shift time of %1.9 ns per bit was achieved, which is below a baseline of 3 ns for typical GST doped with nitrogen/state-of-the-art shift register models using two-terminal-based materials ( Figure S9, Supporting Information).
We take advantage of the strategy utilized for the serial-inserial-out shift register type to propose in Figure 5a, a M state-based shift register configuration capable of performing multiple processing approaches. By combining experimental data and further computing, we can perform more complex procedures, such as serial-in-parallel-out processing schemes. This is made possible by adding the ability to further compute the output resistances of cells. With this new set of functions, one output is represented by the degree of crystallization/ amorphization of the cell obtained using experiments, and computation of the initial resistances of the current stage and previous stage was utilized to represent the second output and third output, respectively ( Figure S17, Supporting Information). For the experimental output, similar to the case in Figure 4, binary outputs "1" and "0" are generated. In output "1," a transition between two different resistance regions (regions I, II, or III in Figure 2a) occurs (large degree of crystallization/amorphization). In output "0," the initial and final resistances stay in the same region (the degree of crystallization/ amorphization is small). For the computed output, the cell configuration that corresponds to the region I/II leads to "1" and the cell configuration corresponding to the region III results in "0." Moreover, the degree of crystallization/amorphization, initial resistances, and cell configurations evolved for the example in which the data sequence "100" is written to the cell (Figure 5b). The write/shift operations are denoted by the colored numbers in Figure 5c. Notably, this work demonstrates the utilization of the M state-based platform for achieving next-generation digital memories and shift registers. This highlights the potential of a programming-driven approach to demonstrate not only multiple-level-per-volt different-initial-state multilevel set process with further computing using the M state-based framework, which has not been demonstrated before, but also previously unreported fast, single-cell, multiple-scheme processing shift register models through M state-based platforms. Additionally, previously unknown M state-based shift register types using different protocols/methodologies were achieved, together with different binary data utilized in M state-based shift register models, which have not been disclosed before. Moreover, more complicated types of modular memristive platforms (a M state-based model framework for both shift register operations and in-memory operation) using all four materials states of PCMs (primed state, partially crystallized states, fully crystalline state, and melt-quenched amorphous state) were achieved. This is in contrast to prior studies that harnessed two/three PC material states (partially crystallized/ crystalline state and amorphous state) to demonstrate the simplest type of reconfigurable memristive systems (logic models using photonic/digital cells). [46][47][48][49][50] Applications such as the machine learning and internet of things are challenging for conventional processors because of several requirements: 1) compact size, 2) fast speed, 3) multiple analog states, and 4) low energy consumption. Currently, the gap in time between the traditional main memory technology and www.advancedsciencenews.com www.advintellsyst.com The details of the statistics can be found in the section Statistical Analysis. The details of the operations for other sequences (e.g., "110," "101," "111") can also be found in Figure S10-S12, Supporting Information.   Table showing evolution of the states in the three bits during operations. The highlighted bits show how the input bit sequence is transferred to the output after three write/shift operations. The details of the operations for other sequences (e.g., "101," "110," "111") can also be found in Figure S14-S16, Supporting Information.
www.advancedsciencenews.com www.advintellsyst.com A key improvement in the M state-based platform to enable these applications is the achievement of single-cell shift register types and also multiple-scheme processing shift register configurations using nonvolatile cells. In traditional nonvolatile systems, for the serial-in-serial-out processing strategy, the operations are performed by a set of memory elements. The inputs of subsequent memory elements are driven by the outputs of preceding ones. However, in this work, it is possible that the M state-based framework can show different cell states, such that the inputs of subsequent states are driven by the outputs of previous ones, resulting in a serial-in-serial-out processing methodology using a single cell. This allows operations to be performed using a smaller number of cells for substantially facilitating device miniaturization. Moreover, conventional nonvolatilebased systems tend to show single processing scheme only (e.g., serial-in-serial-out). On the other hand, the M state-based platform can exhibit multiple processing approaches (e.g., serialin-serial-out, serial-in-parallel-out). This enables more operations to be carried out using the same cell, further enhancing device downscaling.
Additional key advantage is the achievement of short crystallization pulses. A previously-difficult-to-achieve crystallization time of %1.9 ns for conventional nitrogen-doped GST was achieved, which is below the baseline of %3 ns for existing GST cell doped with nitrogen/state-of-the-art nonvolatile-based systems for shift register designs using two-terminal-based materials. This allows operations to be performed in a shorter time for saving operation time. These could open the path to significantly decrease the time needed to transfer data not only between the traditional main memory (DRAM) and conventional storage (flash), but also between the prototypical high-speed/cache memory (register/SRAM) and archetypal main memory (DRAM). The results also provide a way to reduce energy consumption and facilitate device-size reduction.
Another performance advantage can be achieved by having multiple analog states. A previously unachieved multiple-levelper-volt (e.g., three levels per volt) different-initial-state multilevel set process with further computing in the M state-based framework was achieved (the multiple levels at each voltage were realized by using different initial states through moderate bias pulses and with the use of absolute percentage change in resistance as a measure of the level value) (Figure 3b), rather than the traditional single-level-per-volt-only (i.e., one level per volt) same-initial-state pure multilevel set process. These processes enable more data bits to be stored in a single cell for substantially decreasing device size. Moreover, all four material states of PCMs were utilized, which further increases the number of bits stored in a single cell for further enhancing downsizing of devices. An additional advantage can be the achievement of low energy consumption. A low resetting energy (%2.0 pJ) was achieved, which allows the cells to operate with low energies for saving digital computer power.
Further advantage is that the shift register configuration driven by the M state-based platform can facilitate the downscaling of hardware/device size utilized for traditional nonvolatile shift register designs. Conventional magnetic-based shift register designs may rely on the domain wall manipulation and operation using an external magnetic field. [21] On the other hand, the M state-based shift register models do not need external stimulations, which can allow the cells to be incorporated in a smaller hardware for further miniaturization of devices. Furthermore, for traditional magnetic-based shift register designs, the domain wall length/movement limits device length. [51] In contrast, for M state-based shift register types, the movement of the active region is not needed, which enables the use of smaller cells for continued downscaling.
The schematics of cluster-size distribution models (Figure 2c,d) are constructed based on the kinetic theory and several experimental observations in similar material systems that show variations in the change in the resistance for different initial material states (Figure 3a), and simulated evolution of the nuclei-size distribution in the AgInSbTe (AIST), [33,[52][53][54] although a limitation may arise from the limited experimental data in figuring out the detailed shape of the cluster-size distributions. Experiments have demonstrated the use of fluctuation transmission electron microscopy (FTEM), as well as optical (laser pump probe) stimulation measurements, to detect nuclei embedded in a glassy solid in GST/AIST. [32,33] However, quantitative interpretation of the FTEM data for analyzing cluster-size distribution is not well established yet. Nevertheless, general principles adopted in this study have been given from the simulation of the FTEM peak structure, e.g., for a family of amorphous silicon models.
The main limitation to realize the perfect/classical shift register is the limited ensemble of available implementations for the M state-based platform currently. Experiments have demonstrated that traditional memristive state full logic/shift register designs such as the Imply, Magic, and other designs exhibit nonvolatile characters because the resistance state serves as the input and output variables. [24,[55][56][57][58] However, the writing of the initial state and data transfer to other physical locations rely on the conversion of resistance states to electrical signals. Thus, the development of a curated and validated group of controllers for the M state-based framework is of vital importance. These controllers in combination with synthesis tools to control electrical stimuli can expand the accessible device space of the M state-based framework to a wide range of hardware. A further limitation is that it is not possible for the PCM to fill the gap between the DRAM and SRAM in relation to endurance currently. Nevertheless, other researchers are working on extensions that would enable the PCM to fill the gap between the SRAM and DRAM in connection with the endurance through PCM-based cache-design techniques. [59][60][61]

Conclusions
These multiple data storage and register operations are achieved through harnessing all four material states in PCMs. We demonstrate here a combined model framework for in-memory processing architectures based on M state-based platform. By employing an innovative way for realizing a universal shift register based on shift-register-in-memory, we have created reprogrammable, nonvolatile single-cell shift register configurations via the M state-based framework that are performed directly in memory and do not require additional device terminals for programming. This direct integration of the memory function and shift register operation can increase processing speed, opening the way to the realization of energy-efficient hardware based on two-terminal-based materials for machine learning, the internet of things, and nonvolatile memory computing.

Experimental Section
Cell Structure: The PC cell was deposited on a SiO 2 -on-Si substrate, based on our previous cell structure. [46] The cell has a pore-like structure comprising a 25 nm-thick Ge 2 Sb 2 Te 5 layer, which was sandwiched between 300 nm-thick top and bottom TiW electrodes. The Ge 2 Sb 2 Te 5 was confined in the 40 nm-wide pores formed by 25 nm-thick SiO 2 insulating layer. The electrodes were utilized to connect the test structure to the external circuitry for electrical testing, while the silica insulator provides electrical and thermal insulation.
Cell Fabrication and Material Characterization: The PC cell was fabricated using an integrated conventional lithography and nanopatterning technique, according to our previous fabrication protocol. [46,62] Each patterning step comprises using 365 nm photolithography (Cannon) or electron-beam lithography (JEOL), followed by the materials deposition and lift-off process. All of the materials were deposited using composite targets in a DC magnetron sputtering system (Balzers Cube). Nitrogendoped Ge 2 Sb 2 Te 5 (NGST) films were deposited by sputtering from a composite GST target and concurrently in flowing nitrogen gas at a constant N 2 /Ar flow rate of 0.2. The NGST films were characterized using X-ray photoelectron spectroscopy (XPS), which showed that the nitrogen concentration in the film is %3 at%. A 4 00 Si wafer with a 1 μm-thick SiO 2 was utilized as the starting structure, on which a 300 nm-thick TiW bottom electrode was deposited and patterned. An insulating layer, comprising a 25 nm-thick layer of SiO 2 , was deposited and etched to form pores with diameters of %40 nm. The openings were filled with a 25 nm-thick layer of Ge 2 Sb 2 Te 5 for forming the active region. Finally, a 300 nm-thick TiW top electrode was deposited to complete the structure.
Electrical Characterization: The PC cell was characterized using a custom-built electrical characterization system comprising a picosecond (Picosecond Pulse Lab) or nanosecond (Tektronix) pulse generator, a digital oscilloscope (Agilent Technologies), and a probe station, based on our previous testing protocol. The picosecond pulse generator has the specifications of pulse durations ranging from 100 ps to 10 ns, rise time of 65 ps, and maximum amplitude of 7.5 V, and the nanosecond pulse generator has the specifications of the pulse duration varying between 5 and 900 ns, a rise time of less than 3 ns, and a maximum voltage amplitude of 5.0 V. The system is connected to the pulse generator and oscilloscope via low-capacitance cables (%0.2 to 3 pF) and a load resistor of R 1 ¼ 50 Ω. The upper limit of the time constant of the resistance-capacitance circuit is estimated to be several 10 ps. The FWHM time duration of the pulse was measured before the signal passes through the cell and this was utilized to characterize the times of switching in the cells. We have previously investigated and reported the waveform of the voltage pulses obtained before the signal passes through the cell and after the signal passes through the cell. As in those studies, the waveform of the pulse obtained before the signal passes through the cell also reflects the exact voltage pulse that is applied to the system, taking into account the capacitance or inductance of the probe circuitry and connectors. The FWHMs of the waveforms obtained before the signal passes through the cell and after the signal passes through the cell were almost the same. Additionally, as the pulse obtained after the signal passes through the cell has passed through the structure, the duration of the pulse experienced by the cell is almost identical to that of the pulse entering the cell. Furthermore, a comparison of the shapes of the pulses obtained before the signal passes through the cell and after the signal passes through the cell also shows that parasitic capacitance effects in the circuit or structure are negligible, and in the case where they do exist near the end of the pulses, they dissipate with a time with an upper limit of a few nanoseconds, consistent with those reported by other groups. [63,64] We have utilized one of the conventional structure used by many other research groups. [65] The voltage pulse duration needed to switch the large cells was several tens of nanoseconds (depending on the voltage applied), which is about the same as those obtained by other research groups. [66] The duration and height of the voltage pulses were varied from several 100 ps to several 10 ns and from 0 to 7 V, respectively. To ensure good functionality, the cells were switched reversibly more than 100 times between the low resistance level of %40 kΩ and the high resistance level of %350 kΩ before the experimental study. The occurrence of crystallization was determined by the change of the resistance level of the cell. The resistance change of cells with a small pore size was of the "sudden-drop" type and the cell with the large pore size showed similar behavior. This is because the cell utilized the same active material. The resistance of the amorphous state is lower than the typical range of %1 MΩ. This is because a small cell size and a thin phase-change layer was harnessed. The amorphous regions would be smaller and hence the resistance of the amorphous state is lower.
The crystallization process is slower than amorphization and it presents a switching time limitation of PCMs. This time limitation of PCMs has been previously studied. In that work, the origin of the time limitation can be divided into two contributions: 1) crystal nucleation limitation and 2) crystal growth limitation. The maximum crystallization rate of PCMs is determined by the total rates for nucleation (Equation (2)) and growth (Equation (3)) [67] IðtÞ ¼ 4f ð1Þγn (2) where f(1) is the concentration of GST molecules, Z is the Zeldovich factor, γ is the molecular jump frequency at the interface between the amorphous phase and crystalline phase, n c is the maximum number of GST molecules in the cluster, v m is the volume of a GST "molecule," σ is the interfacial energy, Δg is the bulk free-energy difference per GST molecule between the amorphous and crystalline phases, k B is the Boltzmann constant, T is the temperature, τ is the rate of the molecular rearrangement during nucleation, and t is the time.
where D is the diffusion jump frequency of GST molecules, v m is the volume of a GST molecule, k B is the Boltzmann constant, T is the temperature, Δg is the bulk free-energy difference per GST molecule between the amorphous phase and crystalline phase, σ is the interfacial energy, and r is the radius of a cluster. Thermal Simulations: The temperature distribution calculations were performed by finite element methods (FEMs) using the ANSYS software, according to our previous simulation protocol. To study the material state-dependent thermal distribution, we have chosen to utilize a model configuration comprising a 25 nm-thick Ge 2 Sb 2 Te 5 layer sandwiched between 300 nm-thick TiW top and bottom electrodes. The Ge 2 Sb 2 Te 5 layer was also surrounded with a 25 nm-thick SiO 2 insulating layer. The values of the density, specific heat, and thermal conductivity of the SiO 2 were chosen to be 2650 kg m À3 , 703 J kg K À1 , and 1.4 W m À1 K À1 , respectively, while the corresponding values for the Ge 2 Sb 2 Te 5 were 6000 kg m À3 , 202 J kg K À1 , and 0.22 W m À1 K À1 , being intermediate between the values for the crystalline phase and amorphous phase. [68,69] The corresponding values for TiW were selected to be 14 800 kg m À3 , 137 J kg K À1 , and 21.7 W m À1 K À1 , respectively. Furthermore, to investigate the interface dependent thermal diffusion, the thermal resistance at the interface between the SiO 2 and Ge 2 Sb 2 Te 5 was chosen to be between 10 À8 and 10 À10 Wm 2 K À1 , in agreement with other studies. [70,71] Heat transfer was modeled using the heat-conduction equation with heat generation, which was characterized by the Joule heat generated per unit volume per unit time, Q, temperature, T, time, t, density, ρ, specific heat, c, and thermal conductivity, k, expressed as www.advancedsciencenews.com www.advintellsyst.com The thermal distribution of the model was calculated for different resistivities and bias voltages and the material properties were assumed to be independent of temperature.
Statistical Analysis: Figure 2a,b, 3a-e, 4b, 5b, S3,S4, S5b,d,f,h,j, S8b, S10b-S12b, S14b-S16b, Supporting Information, show the resistance achieved by the PC cell for different voltages, programming regions, stages, materials, or pulse types, and Figure 4e discloses the resistance obtained by the PC cell for different biases. The resistance for each voltage, programming region, stage, material, or pulse type was obtained by performing the measurement on 3/6 PC cells with the same voltage, material, or pulse type. Additionally, the pulse length achieved for each bias was obtained by carrying out the measurement on a PC cell for 5 times.
The mean values were calculated from the measurements. The resistance/pulse length achieved by the cells has a variation of AE3% from the mean values.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author.