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dc.contributor.authorNaylor, Matthewen
dc.contributor.authorMoore, Simonen
dc.date.accessioned2015-08-13T13:41:51Z
dc.date.available2015-08-13T13:41:51Z
dc.date.issued2015-08-13en
dc.identifier.urihttps://www.repository.cam.ac.uk/handle/1810/249300
dc.description.abstractWriting test benches is one of the most frequently-performed tasks in the hardware development process. The ability to reuse common test bench features is therefore key to productivity. In this paper, we present a generic test bench, parameterised by a specification of correctness, which can be used to test any design. Our test bench provides several important features, including automatic test-sequence generation and shrinking of counter-examples, and is fully synthesisable, allowing rigorous testing on FPGA as well as in simulation. The approach is easy to use, cheap to implement, and encourages the formal specification of hardware components through the reward of automatic testing and simple failure cases.
dc.description.sponsorshipThis work was supported by DARPA/AFRL contracts FA8750- 10-C-0237 (CTSRD) and FA8750-11-C-0249 (MRC2), and EPSRC grant EP/K008528/1 (REMS).
dc.languageEnglishen
dc.language.isoenen
dc.publisherIEEE
dc.titleA Generic Synthesisable Test Benchen
dc.typeConference Object
dc.description.versionThis is the author accepted manuscript. The final version is available from IEEE via http://dx.doi.org/10.1109/MEMCOD.2015.7340479en
prism.endingPage137
prism.publicationDate2015en
prism.publicationName13th ACM-IEEE International Conference on Formal Methods and Models for System Designen
prism.startingPage128
dc.rioxxterms.funderEPSRC
dc.rioxxterms.projectidEP/K008528/1
rioxxterms.versionofrecord10.1109/MEMCOD.2015.7340479en
rioxxterms.versionAM
rioxxterms.licenseref.urihttp://www.rioxx.net/licenses/all-rights-reserveden
rioxxterms.licenseref.startdate2015-08-13en
dc.contributor.orcidMoore, Simon [0000-0002-2806-495X]
rioxxterms.typeConference Paper/Proceeding/Abstracten
pubs.funder-project-idEPSRC (EP/K008528/1)


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