Show simple item record

dc.contributor.authorNiang, Kham Manen
dc.contributor.authorBarquinha, PMCen
dc.contributor.authorMartins, RFPen
dc.contributor.authorCobb, Ben
dc.contributor.authorPowell, MJen
dc.contributor.authorFlewitt, Andrewen
dc.date.accessioned2016-02-29T12:18:39Z
dc.date.available2016-02-29T12:18:39Z
dc.date.issued2016-03-04en
dc.identifier.issn0003-6951
dc.identifier.urihttps://www.repository.cam.ac.uk/handle/1810/254061
dc.description.abstractThin film transistors(TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and analysed using the thermalization energy concept. The peak energy barrier to defect conversion is extracted to be 0.75 eV and the attempt-to-escape frequency is extracted to be 107 s−1. These values are in remarkable agreement with measurements in a-IGZO TFTs under negative gate bias illumination stress (NBIS) reported recently (Flewitt and Powell, J. Appl. Phys. 115, 134501 (2014)). This suggests that the same physical process is responsible for both PBS and NBIS, and supports the oxygen vacancy defect migration model that the authors have previously proposed.
dc.description.sponsorshipThe research leading to these results has received funding from the European Community’s 7th Framework Programme under grant agreement NMP3-LA-2010-246334. Financial support of the European Commission is therefore gratefully acknowledged. The work has also received funding from FEDER through the COMPETE 2020 Programme and National Funds through FCT–Portuguese Foundation for Science and Technology under the Project No. UID/CTM/50025/2013.
dc.languageEnglishen
dc.language.isoenen
dc.publisherAIP Publishing
dc.rightsAttribution-NonCommercial 2.0 UK: England & Wales*
dc.rights.urihttp://creativecommons.org/licenses/by-nc/2.0/uk/*
dc.titleA thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stressen
dc.typeArticle
dc.provenanceOA-7270
dc.description.versionThis is the author accepted manuscript. The final version is available from AIP Publishing via http://dx.doi.org/10.1063/1.4943249en
prism.number093505en
prism.publicationDate2016en
prism.publicationNameApplied Physics Lettersen
prism.volume108en
rioxxterms.versionofrecord10.1063/1.4943249en
rioxxterms.licenseref.urihttp://www.rioxx.net/licenses/all-rights-reserveden
rioxxterms.licenseref.startdate2016-03-04en
dc.contributor.orcidNiang, Kham Man [0000-0001-5488-6087]
dc.contributor.orcidFlewitt, Andrew [0000-0003-4204-4960]
dc.identifier.eissn1077-3118
rioxxterms.typeJournal Article/Reviewen
pubs.funder-project-idEC FP7 CP (246334)


Files in this item

Thumbnail
Thumbnail

This item appears in the following Collection(s)

Show simple item record

Attribution-NonCommercial 2.0 UK: England & Wales
Except where otherwise noted, this item's licence is described as Attribution-NonCommercial 2.0 UK: England & Wales