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dc.contributor.authorZazo, Jose Fernandoen
dc.contributor.authorLopez-Buedo, Sergioen
dc.contributor.authorAudzevich, Yuryen
dc.contributor.authorMoore, Andrewen
dc.date.accessioned2016-09-22T13:46:36Z
dc.date.available2016-09-22T13:46:36Z
dc.date.issued2016-02-02en
dc.identifier.issn2325-6532
dc.identifier.urihttps://www.repository.cam.ac.uk/handle/1810/260326
dc.description.abstractNetwork Function Virtualization (NFV) allows creating specialized network appliances out of general-purpose computing equipment (servers, storage, and switches). In this paper we present a PCIe DMA engine that allows boosting the performance of virtual network appliances by using FPGA accelerators. Two key technologies are demonstrated, SR-IOV and PCI Passthrough. Using these two technologies, a single FPGA board can accelerate several virtual software appliances. The final goal is, in an NFV scenario, to substitute conventional Ethernet NICs by networking FPGA boards (such as NetFPGA SUME). The advantage of this approach is that FPGAs can very efficiently implement many networking tasks, thus boosting the performance of virtual networking appliances. The SR-IOV capable PCIe DMA engine presented in this work, as well as its associated driver, are key elements in achieving this goal of using FPGA networking boards instead of conventional NICs. Both DMA engine and driver are open source, and target the Xilinx 7-Series and UltraScale PCIe Gen3 endpoint. The design has been tested on a NetFPGA SUME board, offering transfer rates reaching 50 Gb/s for bulk transmissions. By taking advantage of SR-IOV and PCI Passthrough technologies, our DMA engine provides transfers rate well above 40 Gb/s for data transmissions from the FPGA to a virtual machine. We have also identified the bottlenecks in the use of virtualized FPGA accelerators caused by reductions in the maximum read request size and maximum payload PCIe parameters. Finally, the DMA engine presented in this paper is a very compact design, using just 2% of a Xilinx Virtex-7 XC7VX690T device.
dc.description.sponsorshipThis work was partially supported by the Spanish Ministry of Economy and Competitiveness under the project PackTrack (TEC2012-33754) and by the European Union through the Integrated Project (IP) IDEALIST under grant agreement FP7- 317999. The stay of Sergio Lopez-Buedo at the University of Cambridge was funded by the Spanish Government under a ”Jose Castillejo” grant. Additionally, this research was sponsored by EU Horizon 2020 SSICLOPS (agreement No. 644866) research program and EPSRC through Networks as a Service (NaaS) (EP/K034723/1) project.
dc.languageEnglishen
dc.language.isoenen
dc.publisherIEEE
dc.subjectnetwork function virtualizationen
dc.subjectvirtual network applianceen
dc.subjectFPGA-based accelerationen
dc.subjectSR-IOVen
dc.subjectPCI passthroughen
dc.subjectPCIeen
dc.subjectDMA engineen
dc.subjectNetFPGA SUMEen
dc.titleA PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliancesen
dc.typeConference Object
dc.description.versionThis is the author accepted manuscript. The final version is available from IEEE at http://dx.doi.org/10.1109/ReConFig.2015.7393334.en
prism.publicationDate2016en
prism.publicationName2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)en
dc.identifier.doi10.17863/CAM.4557
dcterms.dateAccepted2016-01-01en
rioxxterms.versionofrecord10.1109/ReConFig.2015.7393334en
rioxxterms.versionNAen
rioxxterms.licenseref.urihttp://www.rioxx.net/licenses/all-rights-reserveden
rioxxterms.licenseref.startdate2016-02-02en
dc.contributor.orcidMoore, Andrew [0000-0002-5494-9305]
rioxxterms.typeConference Paper/Proceeding/Abstracten
pubs.funder-project-idEPSRC (EP/K034723/1)


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