Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates.
ACS Appl Mater Interfaces
American Chemical Society
MetadataShow full item record
Zhang, L., Guo, Y., Hassan, V., Tang, K., Foad, M., Woicik, J., Pianetta, P., et al. (2016). Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates.. ACS Appl Mater Interfaces, 8 (29), 19110-19118. https://doi.org/10.1021/acsami.6b03331
Optimization of the interface between high-k dielectrics and SiGe substrates is a challenging topic due to the complexity arising from the coexistence of Si and Ge interfacial oxides. Defective high-k/SiGe interfaces limit future applications of SiGe as a channel material for electronic devices. In this paper, we identify the surface layer structure of as-received SiGe and Al2O3/SiGe structures based on soft and hard X-ray photoelectron spectroscopy. As-received SiGe substrates have native SiOx/GeOx surface layers, where the GeOx-rich layer is beneath a SiOx-rich surface. Silicon oxide regrows on the SiGe surface during Al2O3 atomic layer deposition, and both SiOx and GeOx regrow during forming gas anneal in the presence of a Pt gate metal. The resulting mixed SiOx-GeOx interface layer causes large interface trap densities (Dit) due to distorted Ge-O bonds across the interface. In contrast, we observe that oxygen-scavenging Al top gates decompose the underlying SiOx/GeOx, in a selective fashion, leaving an ultrathin SiOx interfacial layer that exhibits dramatically reduced Dit.
Al2O3, MOSCAP, SiGe, atomic layer deposition, high-k, interface traps
External DOI: https://doi.org/10.1021/acsami.6b03331
This record's URL: https://www.repository.cam.ac.uk/handle/1810/261407