Mono-Type TFT Logic Architectures for Low Power Systems on Panel Applications
Accepted version
Peer-reviewed
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Abstract
This paper introduces novel 7-T pseudo-CMOS for enhancement mode and 6-T pseudo-CMOS for depletion mode inverter circuit architectures. The designs are built around mono-type of TFTs and consume less power consumption than existing 4-T pseudo-CMOS circuits. In addition, they provide steep transfer curves, along with embedded control for compensation of device parameter variations. Analysis of the transient behavior for the various circuit architectures is presented, providing quantitative insight into capacitive loading taking into account the effects of overlap capacitances.
Description
Keywords
inverters, power demand, logic gates, capacitance, thin film transistors, threshold voltage
Journal Title
Journal of Display Technology
Conference Name
Journal ISSN
1551-319X
1558-9323
1558-9323
Volume Title
12
Publisher
IEEE
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Sponsorship
Engineering and Physical Sciences Research Council (EP/M013650/1)
European Commission Horizon 2020 (H2020) Marie Sk?odowska-Curie actions (645760)
European Commission (246334)
European Commission Horizon 2020 (H2020) Research Infrastructures (RI) (692373)
European Commission Horizon 2020 (H2020) Marie Sk?odowska-Curie actions (645760)
European Commission (246334)
European Commission Horizon 2020 (H2020) Research Infrastructures (RI) (692373)