Efficient tagged memory
Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017
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Joannou, A., Woodruff, J., Kovacsics, R., Moore, S., Bradbury, A., Xia, H., Watson, R., et al. (2017). Efficient tagged memory. Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017, 641-648. https://doi.org/10.1109/ICCD.2017.112
We characterize the cache behavior of an in-memory tag table and demonstrate that an optimized implementation can typically achieve a near-zero memory traffic overhead. Both industry and academia have repeatedly demonstrated tagged memory as a key mechanism to enable enforcement of powerful security invariants, including capabilities pointer integrity, watchpoints, and information-flow tracking. A single-bit tag shadowspace is the most commonly proposed requirement, as one bit is the minimum metadata needed to distinguish between an untyped data word and any number of new hardware-enforced types. We survey various tag shadowspace approaches and identify their common requirements and positive features of their implementations. To avoid non-standard memory widths, we identify the most practical implementation for tag storage to be an in-memory table managed next to the DRAM controller. We characterize the caching performance of such a tag table and demonstrate a DRAM traffic overhead below 5\% for the vast majority of applications. We identify spatial locality on a page scale as the primary factor that enables surprisingly high table cache-ability. We then demonstrate tag-table compression for a set of common applications. A hierarchical structure with elegantly simple optimizations reduces DRAM traffic overhead to below 1\% for most applications. These insights and optimizations pave the way for commercial applications making use of single-bit tags stored in commodity memory.
External DOI: https://doi.org/10.1109/ICCD.2017.112
This record's URL: https://www.repository.cam.ac.uk/handle/1810/273303