A maskless etching technique for fabrication of 3D MEMS structures in SOI CMOS devices

Abstract

A maskless etching technique for fabrication of 3D MEMS structures has been presented. The technique has been applied to micro structures embedded during a CMOS process in the dielectric membrane, which was realized by post-CMOS DRIE (deep reactive ion etching) back etch step. A comparison of the conventional etching technique with the developed maskless technique has been presented. The proposed technique takes advantage of the UV (ultra violet) transparent dielectric membrane supporting the CMOS-process based micro structures, where the UV light exposure of the photoresist on the top surface of the device is carried out from the reverse side through the UV-transparent membrane. The surrounding excess membrane is then etched away using suitable anisotropic etching technique such as RIE (reactive ion etching) to release 3D active structures in the CMOS MEMS device. The technique eliminates the requirement of a dedicated photo-mask as the CMOS metallization layer based micro structures are used to transfer the exact pattern on the device surface. Furthermore, expensive mask alignment equipment and skilled human resource is also not required. Thus the reported technique results in overall process simplification, fabrication process time and cost reduction and device yield enhancement. The proposed technique has also been successfully demonstrated to fabricate CMOS MEMS thermal wall shear stress sensors with significantly lower power consumption and stable performance.