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dc.contributor.authorXia, Hongyan
dc.contributor.authorWoodruff, Jonathan
dc.contributor.authorBarral, H
dc.contributor.authorEsswood, Lawrence
dc.contributor.authorJoannou, A
dc.contributor.authorKovacsics, R
dc.contributor.authorChisnall, D
dc.contributor.authorRoe, M
dc.contributor.authorDavis, B
dc.contributor.authorNapierala, Edward
dc.contributor.authorBaldwin, J
dc.contributor.authorGudka, K
dc.contributor.authorNeumann, PG
dc.contributor.authorRichardson, Alexander
dc.contributor.authorMoore, Simon
dc.contributor.authorWatson, Robert
dc.date.accessioned2019-01-12T00:30:10Z
dc.date.available2019-01-12T00:30:10Z
dc.date.issued2018
dc.identifier.isbn9781538684771
dc.identifier.issn1063-6404
dc.identifier.urihttps://www.repository.cam.ac.uk/handle/1810/287872
dc.description.abstractEmbedded systems are deployed ubiquitously among various sectors including automotive, medical, robotics and avionics. As these devices become increasingly connected, the attack surface also increases tremendously; new mechanisms must be deployed to defend against more sophisticated attacks while not violating resource constraints. In this paper we present CheriRTOS on CHERI-64, a hardware-software platform atop Capability Hardware Enhanced RISC Instructions (CHERI) for embedded systems. Our system provides efficient and scalable task isolation, fast and secure inter-task communication, fine-grained memory safety, and real-time guarantees, using hardware capabilities as the sole protection mechanism. We summarize state-of-the-art se- curity and memory safety for embedded systems for comparison with our platform, illustrating the superior substrate provided by CHERI’s capabilities. Finally, our evaluations show that a capability system can be implemented within the constraints of embedded systems.
dc.publisherIEEE
dc.titleCheriRTOS: A Capability Model for Embedded Devices
dc.typeConference Object
prism.endingPage99
prism.publicationDate2019
prism.publicationNameProceedings - 2018 IEEE 36th International Conference on Computer Design, ICCD 2018
prism.startingPage92
dc.identifier.doi10.17863/CAM.26414
dcterms.dateAccepted2018-08-06
rioxxterms.versionofrecord10.1109/ICCD.2018.00023
rioxxterms.versionAM
rioxxterms.licenseref.urihttp://www.rioxx.net/licenses/all-rights-reserved
rioxxterms.licenseref.startdate2019-01-16
dc.contributor.orcidXia, Hongyan [0000-0002-8047-899X]
dc.contributor.orcidRichardson, Alexander [0000-0002-6372-217X]
dc.contributor.orcidMoore, Simon [0000-0002-2806-495X]
rioxxterms.typeConference Paper/Proceeding/Abstract
pubs.funder-project-idEPSRC (1650060)
pubs.funder-project-idEngineering and Physical Sciences Research Council (EP/K008528/1)
pubs.funder-project-idEngineering and Physical Sciences Research Council (1778326)
pubs.conference-name2018 IEEE 36th International Conference on Computer Design (ICCD)
pubs.conference-start-date2018-10-07
cam.orpheus.successThu Nov 05 11:53:18 GMT 2020 - Embargo updated
pubs.conference-finish-date2018-10-10
rioxxterms.freetoread.startdate2020-01-16


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