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dc.contributor.authorNaylor, Matthewen
dc.contributor.authorMoore, Simonen
dc.contributor.authorThomas, Daviden
dc.date.accessioned2019-07-19T13:50:56Z
dc.date.available2019-07-19T13:50:56Z
dc.identifier.issn1946-1488
dc.identifier.urihttps://www.repository.cam.ac.uk/handle/1810/294801
dc.description.abstractCommodity FPGA boards with advanced networking facilities have great potential in the construction of high-performance compute clusters that scale. However, low-level design tools and long synthesis times are major barriers to productivity for application developers. In this paper, we explore the potential of a distributed soft-processor overlay, programmed in software at a high-level of abstraction, to deliver a useful level of performance for FPGA clusters. In particular, we demonstrate the use of hardware multhreading to achieve a fast, space-efficient, high-throughput overlay, and compare a 12-FPGA instance of it (12,288 RISC-V threads) against a conventional Xeon cluster on the problem of distributed graph processing.
dc.description.sponsorshipThis work was supported by EPSRC grant EP/N031768/1 (POETS project).
dc.publisherIEEE
dc.titleTinsel: a manythread overlay for FPGA clustersen
dc.typeConference Object
prism.publicationName2019 29th International Conference on Field Programmable Logic and Applications (FPL)en
dc.identifier.doi10.17863/CAM.41892
dcterms.dateAccepted2019-05-17en
rioxxterms.versionofrecord10.1109/FPL.2019.00066en
rioxxterms.versionAM*
rioxxterms.licenseref.urihttp://www.rioxx.net/licenses/all-rights-reserveden
rioxxterms.licenseref.startdate2019-05-17en
dc.contributor.orcidMoore, Simon [0000-0002-2806-495X]
rioxxterms.typeConference Paper/Proceeding/Abstracten
pubs.funder-project-idUNIVERSITY OF SOUTHAMPTON (FB EPSRC) (EP/N031768/1)
cam.issuedOnline2019-11-07en
pubs.conference-name2019 International Conference on Field Programmable Logic and Applicationsen
pubs.conference-start-date2019-09-09en


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