jats:pGaN-on-Si is a lateral technology and as such it allows the integration of high voltage High Electron Mobility Transistors and low voltage devices on the same chip, thus enabling the miniaturization and reduction of parasitic inductances. Due to the fact that integrated devices share a common substrate, the performance of one device can be significantly affected by the operation of another. The choice of the substrate bias is particularly important in the integrated half-bridge, a popular topology which includes a low- and a high-side device. A grounded substrate will cause vertical stress on the high-side device, while a floating substrate will couple with the high voltage, resulting in stress on the low-side device. This is highly problematic as the devices may fail to turn on or have a significantly increased RON. In this work, we carefully investigate the substrate coupling of a high-side and low-side device via backgating measurements. We demonstrate that the unwanted RON increase in the high side device could be suppressed by hole injection from the gate, if the gate is formed of a p-type material.</jats:p>