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Vector Runahead for Indirect Memory Accesses

Accepted version
Peer-reviewed

Type

Article

Change log

Abstract

Vector runahead delivers extremely high memory-level parallelism even for the chains of dependent memory accesses with complex intermediate address computation, which conventional runahead techniques fundamentally cannot handle and, therefore, have ignored. It does this by rearchitecting runahead to use speculative data-level parallelism, rather than work skipping, as its primary form of extracting more memory-level parallelism in runahead mode than a true execution can, which we hope will bring about an entirely new dimension for high-performance processors.

Description

Keywords

4606 Distributed Computing and Systems Software, 46 Information and Computing Sciences, 40 Engineering, 4009 Electronics, Sensors and Digital Hardware

Journal Title

IEEE Micro

Conference Name

Journal ISSN

0272-1732
1937-4143

Volume Title

42

Publisher

Institute of Electrical and Electronics Engineers (IEEE)
Sponsorship
Engineering and Physical Sciences Research Council (EP/P020011/1)