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Research data supporting "Enhancing the L1 Data Cache Design to Mitigate HCI"

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datacite.iscitedby.urlhttps://www.repository.cam.ac.uk/handle/1810/249106
datacite.issupplementto.doi10.1109/LCA.2015.2460736
dc.contributor.authorValero, Alejandro
dc.contributor.authorMiralaei, Negar
dc.contributor.authorPetit, Salvador
dc.contributor.authorSahuquillo, Julio
dc.contributor.authorJones, Timothy M.
dc.contributor.orcidJones, Timothy M. [0000-0002-4114-7661]
dc.date.accessioned2015-07-22T09:49:41Z
dc.date.available2015-07-22T09:49:41Z
dc.date.issued2015-07-22
dc.descriptionSimulator code, input files and example command lines to evaluate two techniques for reducing HCI ageing in processor caches. This dataset supports the article published by IEEE at http://dx.doi.org/10.1109/LCA.2015.2460736. A version of this article is stored on the repository at https://www.repository.cam.ac.uk/handle/1810/249106 .en
dc.description.sponsorshipEPSRC Otheren
dc.formatTexten
dc.identifier.doi10.17863/CAM.69224
dc.identifier.urihttps://www.repository.cam.ac.uk/handle/1810/249006
dc.publisherUniversity of Cambridgeen
dc.rightsAll Rights Reserveden
dc.rights.urihttps://www.rioxx.net/licenses/all-rights-reserved/en
dc.rioxxterms.funderEPSRC
dc.rioxxterms.funderEPSRC
dc.rioxxterms.funderFEDER
dc.rioxxterms.funderEU-FP7-ICT
dc.rioxxterms.projectidEP/K026399/1
dc.rioxxterms.projectidEP/J016284/1
dc.rioxxterms.projectidTIN2012-38341-C04-01
dc.rioxxterms.projectidEU FP7-ICT: 287759
dc.subjectData Cacheen
dc.subjectHCIen
dc.subjectAgeingen
dc.titleResearch data supporting "Enhancing the L1 Data Cache Design to Mitigate HCI"en
dc.typeDataseten
dcterms.formattxt
pubs.declined2017-10-11T13:54:39.410+0100

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