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Promoting Low-Voltage Saturation in High-Performance a-InGaZnO Source-Gated Transistors

Accepted version
Peer-reviewed

Type

Article

Change log

Abstract

As oxide semiconductors increase in popularity with emerging flexible electronics, advances in material performance may lead to parasitic and non-ideal effects becoming more prominent. Specifically, in source-gated transistors, and other contact-controlled devices, the influence of the lateral drain field produced by drain bias leads to an overwhelming increase in charge density at the source edge and obliterates their signature flat saturation at low drain voltages. Here, we present high current density amorphous InGaZnO (a-IGZO) source-gated transistors (SGTs) in a bottom contact architecture using Pt source and drain electrodes. The devices were fabricated by ensuring an oxygen-rich atmosphere to prevent the formation of oxygen vacancies at the Pt/a-IGZO interface. Incorporating a field relief structure within the source contact improves drain current saturation, towards behavior predicted by the saturation coefficient. In the device architecture considered, the screening was less effective for a field plate insulator thickness under 30 nm, possibly due to increased tunnelling. Field plate incorporation is one of the strategies that ensures flat saturation and the suitability of contact-controlled transistors for a multitude of current driving and amplification applications.

Description

Keywords

40 Engineering, 4016 Materials Engineering, 4018 Nanotechnology

Journal Title

IEEE Transactions on Electron Devices

Conference Name

Journal ISSN

0018-9383
1557-9646

Volume Title

Publisher

Institute of Electrical and Electronics Engineers (IEEE)
Sponsorship
EPSRC (EP/W009757/1)