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Symmetric Circuits for Rank Logic.

dc.contributor.authorDawar, Anuj
dc.contributor.authorWilsenach, Gregory
dc.contributor.editorGhica, DR
dc.contributor.editorJung, A
dc.contributor.orcidDawar, Anuj [0000-0003-4014-8248]
dc.date.accessioned2018-11-21T00:30:46Z
dc.date.available2018-11-21T00:30:46Z
dc.date.issued2018
dc.identifier.doi10.17863/CAM.32873
dc.identifier.isbn978-3-95977-088-0
dc.identifier.urihttps://www.repository.cam.ac.uk/handle/1810/285515
dc.language.isoeng
dc.publisherSchloss Dagstuhl - Leibniz-Zentrum für Informatik
dc.publisher.urlhttp://www.dagstuhl.de/dagpub/978-3-95977-088-0
dc.rightsAttribution 4.0 International
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/
dc.titleSymmetric Circuits for Rank Logic.
dc.typeConference Object
prism.endingPage20:1
prism.publicationDate2018
prism.publicationNameCSL
prism.startingPage20:1
prism.volume119
rioxxterms.licenseref.startdate2018
rioxxterms.licenseref.urihttp://www.rioxx.net/licenses/all-rights-reserved
rioxxterms.typeConference Paper/Proceeding/Abstract
rioxxterms.versionVoR
rioxxterms.versionofrecord10.17863/CAM.32873

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