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Encapsulation of graphene transistors and vertical device integration by interface engineering with atomic layer deposited oxide

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Alexander-Webber, JA 
Sagade, AA 
Aria, AI 
Van Veldhoven, ZA 
Braeuninger-Weimer, Philipp  ORCID logo


We demonstrate a simple, scalable approach to achieve encapsulated graphene transistors with negligible gate hysteresis, low doping levels and enhanced mobility compared to as-fabricated devices. We engineer the interface between graphene and atomic layer deposited (ALD) Al2O3 by tailoring the growth parameters to achieve effective device encapsulation whilst enabling the passivation of charge traps in the underlying gate dielectric. We relate the passivation of charge trap states in the vicinity of the graphene to conformal growth of ALD oxide governed by in situ gaseous H2O pretreatments. We demonstrate the long term stability of such encapsulation techniques and the resulting insensitivity towards additional lithography steps to enable vertical device integration of graphene for multi-stacked electronics fabrication.



graphene, atomic layer deposition, device integration, hysteresis, air stability, Al$_{2}$O$_{3}$

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2D Materials

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Institute of Physics
Engineering and Physical Sciences Research Council (EP/K016636/1)
European Research Council (279342)
Engineering and Physical Sciences Research Council (EP/L020963/1)
Engineering and Physical Sciences Research Council (EP/L016087/1)
Engineering and Physical Sciences Research Council (EP/M506485/1)
This work was supported by the EPSRC (Grant Nos. EP/K016636/1, GRAPHTED and EP/L020963/1) and the ERC (Grant No. 279342, InsituNANO). JAA-W acknowledges a Research Fellowship from Churchill College, Cambridge. JS acknowledges support from NUDT. ZAVV acknowledges funding from ESPRC grant EP/L016087/1. ACV acknowledges the Conacyt Cambridge Scholarship and the Roberto Rocca Fellowship. RW acknowledges EPSRC Doctoral Training Award (EP/M506485/1).