A generic synthesisable test bench
Accepted version
Peer-reviewed
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Repository DOI
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Authors
Naylor, M
Moore, Simon https://orcid.org/0000-0002-2806-495X
Abstract
Writing test benches is one of the most frequently-performed tasks in the hardware development process. The ability to reuse common test bench features is therefore key to productivity. In this paper, we present a generic test bench, parameterised by a specification of correctness, which can be used to test any design. Our test bench provides several important features, including automatic test-sequence generation and shrinking of counter-examples, and is fully synthesisable, allowing rigorous testing on FPGA as well as in simulation. The approach is easy to use, cheap to implement, and encourages the formal specification of hardware components through the reward of automatic testing and simple failure cases.
Description
Keywords
46 Information and Computing Sciences, 4612 Software Engineering, Generic health relevance
Journal Title
2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2015
Conference Name
2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)
Journal ISSN
Volume Title
Publisher
IEEE
Publisher DOI
Sponsorship
Engineering and Physical Sciences Research Council (EP/K008528/1)
This work was supported by DARPA/AFRL contracts FA8750-
10-C-0237 (CTSRD) and FA8750-11-C-0249 (MRC2), and
EPSRC grant EP/K008528/1 (REMS).