Expansibility Evaluation of a Two-dimensional Access Array for Quantum Computing
The main challenge in quantum computing is not how to make qubits, but how to make a lot of them. Especially, the one-qubit-one-input approach is unsustainable for higher numbers. This issue has already been resolved in classical computing, and I investigate a similar solution for quantum. I evaluate the expansibility prospects of a multiplexing chip: a two-dimensional access array, designed to combat this very problem. First, I characterize on-chip integrated transistors. I list their standard transport parameters, such as threshold voltage, subthreshold swing, and drain induced barrier lowering. Additionally, I report Coulomb oscillations and the formation of quantum dots in 40 nm commercially-available MOSFET devices. I benchmark those against a finFET of the same dimensions, designed for quantum operation. I reflect on the readiness of industrial CMOS devices for use in quantum computing. Then, I assess the operation of control transistors in a memory cell structure. I analyze retention times and comment on their usability for a refresh mechanism and time-multiplexed access to quantum information. Afterward, I demonstrate the mechanism of gate-based reflectometry readout. I detail the RF circuitry, including the room-temperature equipment, and the on-chip analog LC resonators. I present my findings on tuning individual parameters, and their impact on the signal quality, quantitatively depicted by the signal-to-noise ratio and Q factor comparison. I explain the difficulties faced with managing the readout at several GHz, and some other challenges, including parasitics-induced frequency shift and overlap. Finally, I demonstrate time- and frequency-domain multiplexing for an integrated array, as well as two different cointegrated architectures.