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dc.contributor.authorLai, Chongxien
dc.date.accessioned2020-12-03T09:37:49Z
dc.date.available2020-12-03T09:37:49Z
dc.date.submitted2020-07-02en
dc.identifier.urihttps://www.repository.cam.ac.uk/handle/1810/313960
dc.description.abstractThis thesis describes the development of a system that can assign identities to a population of single-units, in multi-electrode recordings, at single-spike resolution with low-latency. The system has two parts. The first is a Field-Programmable Gate Array (FPGA)-based Neural Signal Processor (NSP) that receives raw input and generates labelled spikes as output, a process referred to as real-time spike inference. The second is a piece of software (Spiketag) that runs on a PC, communicates with the NSP, and generates a spike-sorted model to guide the real-time spike inference. The NSP provides clocks and control signals to five 32-channel INTAN RHD2132 chips to manage the acquisition of 160 channels of raw neural data. In parallel, the NSP further filters, detects and extracts extracellular spike waveforms from the raw neural data recorded by tetrodes or silicon probes and assigns single-unit identity to each detected spike. A set of Python application programming interfaces (APIs) was developed in Spiketag to enable the communication between the NSP and the PC. These APIs allow the NSP to obtain a model from the PC, which holds parameters such as reference channels, spike detection thresholds, spike feature transformation matrix and vector quantized clusters generated by spike sorting a short recording session. Using the spike-sorted model, the NSP performs data acquisition and real-time spike inference simultaneously. Algorithmic modules were implemented in the FPGA and pipelined to compute during 40 ms acquisition intervals. At the output end of the FPGA NSP, the real-time assigned single-unit identity (spike-id) is packaged with the timestamp, the electrode group, and the spike features as a spike-id packet. Spike-id packets are asynchronously transmitted through a low-latency Peripheral Component Interconnect Express (PCIe) interface to the PC, producing the real-time spike trains. The real-time spike trains can be used for further processing, such as real-time decoding. Several types of ground-truth data, including intracellular/extracellular paired recordings, synthesized tetrode extracellular waveforms with ground-truth spike timing and high-channel-count silicon probe recordings with ground-truth animal positions during navigation were used to validate the low-latency (1 ms) and high-accuracy (as high as state-of-the-art offline sorting and decoding algorithms) of the NSP’s real-time spike inference and the NSP-based real-time population decoding performance.en
dc.rightsAll rights reserveden
dc.rightsAll rights reserveden
dc.rightsAll rights reserveden
dc.rightsAll rights reserveden
dc.subjectNeural Signal Processoren
dc.subjectFPGAen
dc.subjectReal-time Spike Sortingen
dc.subjectReal-time Decodingen
dc.subjectTemporal codeen
dc.subjectLow-latency spike identificationen
dc.subjectMulti-electrode recordingen
dc.subjectOn-chip neural signal processingen
dc.subjectHardware-Software codesignen
dc.subjectProgressive Visual Analyticsen
dc.subjectOpenGLen
dc.subjectBrain Machine Interfaceen
dc.subjectBrain Computer Interfaceen
dc.titleA Neural Signal Processor for Low-Latency Spike Inferenceen
dc.typeThesis
dc.type.qualificationlevelDoctoralen
dc.type.qualificationnameDoctor of Philosophy (PhD)en
dc.publisher.institutionUniversity of Cambridgeen
dc.identifier.doi10.17863/CAM.61063
rioxxterms.licenseref.urihttp://www.rioxx.net/licenses/all-rights-reserveden
rioxxterms.typeThesisen
dc.publisher.collegeClare Hall
dc.type.qualificationtitlePhDen
cam.supervisorPaulsen, Ole
rioxxterms.freetoread.startdate2021-12-03


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