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dc.contributor.authorValero, Aen
dc.contributor.authorMiralaei, Negaren
dc.contributor.authorPetit, Sen
dc.contributor.authorSahuquillo, Jen
dc.contributor.authorJones, Timothy M.en
dc.date.accessioned2017-01-18T11:23:58Z
dc.date.available2017-01-18T11:23:58Z
dc.date.issued2017-03-01en
dc.identifier.issn1063-8210
dc.identifier.urihttps://www.repository.cam.ac.uk/handle/1810/261910
dc.description.abstractHot carrier injection (HCI) and bias temperature instability (BTI) are two of the main deleterious effects that increase a transistor's threshold voltage over the lifetime of a microprocessor. This voltage degradation causes slower transistor switching and eventually can result in faulty operation. HCI manifests itself when transistors switch from logic ''0'' to ''1'' and vice versa, whereas BTI is the result of a transistor maintaining the same logic value for an extended period of time. These failure mechanisms are especiall in those transistors used to implement the SRAM cells of first-level (L1) caches, which are frequently accessed, so they are critical to performance, and they are continuously aging. This paper focuses on microarchitectural solutions to reduce transistor aging effects induced by both HCI and BTI in the data array of L1 data caches. First, we show that the majority of cell flips are concentrated in a small number of specific bits within each data word. In addition, we also build upon the previous studies, showing that logic ''0'' is the most frequently written value in a cache by identifying which cells hold a given logic value for a significant amount of time. Based on these observations, this paper introduces a number of architectural techniques that spread the number of flips evenly across memory cells and reduce the amount of time that logic ''0'' values are stored in the cells by switching
dc.description.sponsorshipThis work was supported in part by the Spanish Ministerio de Economía y Competitividad within the Plan E Funds under Grant TIN2015-66972-C5-1-R, in part by the HiPEAC Collaboration Grant funded by the FP7 HiPEAC Network of Excellence under Grant 287759, and in part by the Engineering and Physical Sciences Research Council under Grant EP/K 026399/1 and Grant EP/J016284/1.
dc.languageEnglishen
dc.language.isoenen
dc.publisherIEEE
dc.titleOn microarchitectural mechanisms for cache wearout reductionen
dc.typeArticle
prism.endingPage871
prism.publicationDate2017en
prism.publicationNameIEEE Transactions on Very Large Scale Integration (VLSI) Systemsen
prism.startingPage857
prism.volume25en
dc.identifier.doi10.17863/CAM.7147
dcterms.dateAccepted2016-10-21en
rioxxterms.versionofrecord10.1109/TVLSI.2016.2625809en
rioxxterms.versionAMen
rioxxterms.licenseref.urihttp://www.rioxx.net/licenses/all-rights-reserveden
rioxxterms.licenseref.startdate2017-03-01en
dc.contributor.orcidJones, Timothy M. [0000-0002-4114-7661]
dc.identifier.eissn1557-9999
rioxxterms.typeJournal Article/Reviewen
pubs.funder-project-idEPSRC (EP/J016284/1)
pubs.funder-project-idEPSRC (EP/K026399/1)


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