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dc.contributor.authorZhao, Yirenen
dc.contributor.authorGao, Xen
dc.contributor.authorGuo, Xuanen
dc.contributor.authorLiu, Jen
dc.contributor.authorWang, Een
dc.contributor.authorMullins, Roberten
dc.contributor.authorCheung, PYKen
dc.contributor.authorConstantinides, Gen
dc.contributor.authorXu, CZen
dc.date.accessioned2019-11-29T00:30:54Z
dc.date.available2019-11-29T00:30:54Z
dc.date.issued2019-12-01en
dc.identifier.isbn9781728129433en
dc.identifier.urihttps://www.repository.cam.ac.uk/handle/1810/299439
dc.description.abstractModern deep Convolutional Neural Networks (CNNs) are computationally demanding, yet real applications often require high throughput and low latency. To help tackle these problems, we propose Tomato, a framework designed to automate the process of generating efficient CNN accelerators. The generated design is pipelined and each convolution layer uses different arithmetics at various precisions. Using Tomato, we showcase state-of-the-art multi-precision multi-arithmetic networks, including MobileNet-V1, running on FPGAs. To our knowledge, this is the first multi-precision multi-arithmetic auto-generation framework for CNNs. In software, Tomato fine-tunes pretrained networks to use a mixture of short powers-of-2 and fixed-point weights with a minimal loss in classification accuracy. The fine-tuned parameters are combined with the templated hardware designs to automatically produce efficient inference circuits in FPGAs. We demonstrate how our approach significantly reduces model sizes and computation complexities, and permits us to pack a complete ImageNet network onto a single FPGA without accessing off-chip memories for the first time. Furthermore, we show how Tomato produces implementations of networks with various sizes running on single or multiple FPGAs. To the best of our knowledge, our automatically generated accelerators outperform closest FPGA-based competitors by at least 2-4x for lantency and throughput; the generated accelerator runs ImageNet classification at a rate of more than 3000 frames per second.
dc.description.sponsorshipEPSRC Doctoral Scholarship Peterhouse Graduate Studentship
dc.rightsAll rights reserved
dc.rights.uri
dc.titleAutomatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAsen
dc.typeConference Object
prism.endingPage53
prism.publicationDate2019en
prism.publicationNameProceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019en
prism.startingPage45
prism.volume2019-Decemberen
dc.identifier.doi10.17863/CAM.46508
dcterms.dateAccepted2019-09-29en
rioxxterms.versionofrecord10.1109/ICFPT47387.2019.00014en
rioxxterms.versionAM
rioxxterms.licenseref.urihttp://www.rioxx.net/licenses/all-rights-reserveden
rioxxterms.licenseref.startdate2019-12-01en
dc.contributor.orcidZhao, Yiren [0000-0002-3727-7463]
dc.contributor.orcidGuo, Xuan [0000-0001-8677-3298]
dc.contributor.orcidMullins, Robert [0000-0002-8393-2748]
rioxxterms.typeConference Paper/Proceeding/Abstracten
cam.orpheus.successThu Nov 05 11:55:12 GMT 2020 - Embargo updated*
rioxxterms.freetoread.startdate2020-12-01


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