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Randomized Testing of RISC-V CPUs Using Direct Instruction Injection

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TestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in the Sail language, giving a human-readable specification that can also be used for simulation and verification. The Sail language is designed for this purpose by allowing instruction semantics to be described conveniently (for example, by supporting variable bit-widths). Ideally, a RISC-V implementor could formally prove equivalence between their implementation and the Sail model, but proof tools are not yet sufficiently automated to be routinely used on the whole- processor level. They instead focus on equivalence between combinational logic functions, with verification of a full out-of-order microarchitecture remaining an open problem. As a pragmatic compromise, we use TestRIG to check equivalence between the model and an implementation by generating random instruction sequences, executing the same sequences on the model and the implementation under test, and comparing execution traces (tandem execution). This approach does not prove equivalence but can demonstrate divergence, and is usable in all stages of development.



40 Engineering, 4009 Electronics, Sensors and Digital Hardware

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IEEE Design and Test

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Institute of Electrical and Electronics Engineers (IEEE)
EPSRC (EP/K503757/1)
Engineering and Physical Sciences Research Council (EP/K008528/1)
Sponsored by the United States Defense Advanced Research Projects Agency (DARPA), under contract HR0011-18-C-0016 (“ECATS”) as part of the DARPA SSITH research program. Also, IOSec (RG90973), SIPP (G101309) and DSbD (G102946).