Randomized Testing of RISC-V CPUs Using Direct Instruction Injection

Editor’s notes: This article presents a randomized testing framework for RISC-V implementations by using a technique called direct instruction injection for test injection. —Fei Su, Intel, USA

Keywords

40 Engineering, 4009 Electronics, Sensors and Digital Hardware

Journal Title

IEEE Design and Test

Journal ISSN

2168-2356
2168-2364

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Publisher DOI

https://doi.org/10.1109/mdat.2023.3262741

Rights and licensing

Except where otherwised noted, this item's license is described as Attribution 4.0 International

Sponsorship

EPSRC (EP/K503757/1)
Engineering and Physical Sciences Research Council (EP/K008528/1)
Innovate UK (105694)

Sponsored by the United States Defense Advanced Research Projects Agency (DARPA), under contract HR0011-18-C-0016 (“ECATS”) as part of the DARPA SSITH research program. Also, IOSec (RG90973), SIPP (G101309) and DSbD (G102946).

Collections

University of Cambridge Research Outputs (Articles and Conferences)