InAs nanowire transistor pairs as NMOS inverters.

Abstract

III-V semiconductor nanowires have the potential to play a key role in compact and flexible electronic devices for low-power applications. Here, we integrate pairs of InAs nanowires in an inverter configuration for NMOS logic circuit applications. By controlling the nanowire diameter and channel length with a combination of growth and device design, we can control the threshold voltage of each transistor of the device. Smaller diameter (<50 nm) nanowires operate in enhancement mode whereas larger diameters operate in depletion mode. Using these controllable transistor characteristics we fabricate inverter circuits with pairs of nanowires. We optimise the inverter voltage transfer characteristics by controlling the channel and gate geometries and by reducing the gate dielectric thickness. The gate length determines the inverter's switching voltage, which can be made symmetric about zero volts. The optimised inverter device can achieve a full rail-to-rail output voltage swing and switching ratio of 99.3%, with an RC-limited frequency response. The gain value and extracted high and low noise margins of 42% and 32%, respectively, satisfy the requirements for the inverter to be used in cascaded logic circuits.