Integrated photonic iterative processor for I/O-efficient computing: Selecting the optimal core processing architecture

Integrated photonic iterative processor for I/O-efficient computing: Selecting the optimal core processing architecture

Accepted version

Peer-reviewed

Repository URI

https://www.repository.cam.ac.uk/handle/1810/394300

Repository DOI

https://doi.org/10.17863/CAM.124334

Files

Primary Accepted version (1.02 MB)

Type

Conference Object

Authors

Wonfor, Adrian

https://orcid.org/0000-0003-2219-7900

Yang, Shuai

https://orcid.org/0000-0003-3572-516X

Abstract

Photonic iterative processors can surpass the input/output bottleneck by directly reusing input data in the optical domain. We provide guidelines for selecting the optimal core processing architecture to ensure peak performance across various scenarios.

Keywords

33 Built Environment and Design, 40 Engineering, 3301 Architecture

Journal Title

CLEO 2025

Conference Name

CLEO 2025

Publisher

Optica Publishing Group

Publisher DOI

https://doi.org/10.1364/cleo_si.2025.ss184_5

Rights and licensing

Attribution 4.0 International

Except where otherwised noted, this item's license is described as Attribution 4.0 International

Collections

University of Cambridge Research Outputs (Articles and Conferences)