Rapid codesign of a soft vector processor and its compiler
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Naylor, M., & Moore, S. (2014). Rapid codesign of a soft vector processor and its compiler. https://doi.org/10.1109/FPL.2014.6927425
Despite a decade of activity in the development of soft vector processors for FPGAs, high-level language support remains thin. We attribute this problem to a design method in which the high-level vector programming interface is only really considered once the processor architecture has been perfected, by which point the designer may be committed to the timeconsuming development of a complicated compiler. In this paper, we present the codesign of a soft vector processor and a lightweight compiler, which together lift the level of abstraction for the programmer while allowing a rapid compiler implementation phase.We demonstrate the effectiveness of our approach on a range of applications from digital signal processing, neuroscience, and machine learning.
This work is sponsored by EPSRC grant EP/G015783/1.
External DOI: https://doi.org/10.1109/FPL.2014.6927425
This record's URL: https://www.repository.cam.ac.uk/handle/1810/245701