HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs
ACM SIGARCH Computer Architecture News - ISCA '14
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Campanoni, S., Brownell, K., Kanev, S., Jones, T. M., Wei, G., & Brooks, D. (2014). HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs. ACM SIGARCH Computer Architecture News - ISCA '14, 42 217-228. https://doi.org/10.1145/2678373.2665705
Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with a parallelizing compiler, which together can decouple communication from thread execution. Simulations of these approaches, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85 performance speedup for six SPEC CINT2000 benchmarks.
This work was possible thanks to the sponsorship of the Royal Academy of Engineering, EPSRC and the National Science Foundation (award number IIS-0926148).
External DOI: https://doi.org/10.1145/2678373.2665705
This record's URL: https://www.repository.cam.ac.uk/handle/1810/246957