A Generic Synthesisable Test Bench
13th ACM-IEEE International Conference on Formal Methods and Models for System Design
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Naylor, M., & Moore, S. (2015). A Generic Synthesisable Test Bench. 13th ACM-IEEE International Conference on Formal Methods and Models for System Design, 128-137. https://doi.org/10.1109/MEMCOD.2015.7340479
Writing test benches is one of the most frequently-performed tasks in the hardware development process. The ability to reuse common test bench features is therefore key to productivity. In this paper, we present a generic test bench, parameterised by a specification of correctness, which can be used to test any design. Our test bench provides several important features, including automatic test-sequence generation and shrinking of counter-examples, and is fully synthesisable, allowing rigorous testing on FPGA as well as in simulation. The approach is easy to use, cheap to implement, and encourages the formal specification of hardware components through the reward of automatic testing and simple failure cases.
This work was supported by DARPA/AFRL contracts FA8750- 10-C-0237 (CTSRD) and FA8750-11-C-0249 (MRC2), and EPSRC grant EP/K008528/1 (REMS).
External DOI: https://doi.org/10.1109/MEMCOD.2015.7340479
This record's URL: https://www.repository.cam.ac.uk/handle/1810/249300