Tinsel: a manythread overlay for FPGA clusters
2019 29th International Conference on Field Programmable Logic and Applications (FPL)
2019 International Conference on Field Programmable Logic and Applications
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Naylor, M., Moore, S., & Thomas, D. (2019). Tinsel: a manythread overlay for FPGA clusters. 2019 29th International Conference on Field Programmable Logic and Applications (FPL) https://doi.org/10.1109/FPL.2019.00066
Commodity FPGA boards with advanced networking facilities have great potential in the construction of high-performance compute clusters that scale. However, low-level design tools and long synthesis times are major barriers to productivity for application developers. In this paper, we explore the potential of a distributed soft-processor overlay, programmed in software at a high-level of abstraction, to deliver a useful level of performance for FPGA clusters. In particular, we demonstrate the use of hardware multhreading to achieve a fast, space-efficient, high-throughput overlay, and compare a 12-FPGA instance of it (12,288 RISC-V threads) against a conventional Xeon cluster on the problem of distributed graph processing.
Is supplemented by: https://doi.org/10.17863/CAM.40123
This work was supported by EPSRC grant EP/N031768/1 (POETS project).
Engineering and Physical Sciences Research Council (EP/N031768/1)
External DOI: https://doi.org/10.1109/FPL.2019.00066
This record's URL: https://www.repository.cam.ac.uk/handle/1810/294801