Robust In-Zn-O Thin-Film Transistors with a Bilayer Heterostructure Design and a Low-Temperature Fabrication Process Using Vacuum and Solution Deposited Layers.
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We report on the design, fabrication, and characterization of heterostructure In-Zn-O (IZO) thin-film transistors (TFTs) with improved performance characteristics and robust operation. The heterostructure layer is fabricated by stacking a solution-processed IZO film on top of a buffer layer, which is deposited previously using an electron beam (e-beam) evaporator. A thin buffer layer at the dielectric interface can help to template the structure of the channel. The control of the precursors and of the solvent used during the sol-gel process can help lower the temperature needed for the sol-gel condensation reaction to proceed cleanly. This boosts the overall performance of the device with a significantly reduced subthreshold swing, a four-fold mobility increase, and a two-order of magnitude larger on/off ratio. Atomistic simulations of the a-IZO structure using molecular dynamics (both classical and ab initio) and hybrid density functional theory (DFT) calculations of the electronic structure reveal the potential atomic origin of these effects.
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2470-1343
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Engineering and Physical Sciences Research Council (EP/P027628/1)
European Commission Horizon 2020 (H2020) Research Infrastructures (RI) (685758)