Vector Runahead for Indirect Memory Accesses
Accepted version
Peer-reviewed
Repository URI
Repository DOI
Change log
Abstract
Vector runahead delivers extremely high memory-level parallelism even for the chains of dependent memory accesses with complex intermediate address computation, which conventional runahead techniques fundamentally cannot handle and, therefore, have ignored. It does this by rearchitecting runahead to use speculative data-level parallelism, rather than work skipping, as its primary form of extracting more memory-level parallelism in runahead mode than a true execution can, which we hope will bring about an entirely new dimension for high-performance processors.
Description
Journal Title
IEEE Micro
Conference Name
Journal ISSN
0272-1732
1937-4143
1937-4143
Volume Title
42
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
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Rights and licensing
Except where otherwised noted, this item's license is described as Attribution 4.0 International
Sponsorship
Engineering and Physical Sciences Research Council (EP/P020011/1)
EPSRC (EP/W00576X/1)
EPSRC (EP/W00576X/1)

