CHERI: Hardware-Enabled C/C++ Memory Protection at Scale
Accepted version
Peer-reviewed
Repository URI
Repository DOI
Change log
Abstract
The memory-safe CHERI C and C++ languages build on architectural capabilities in the CHERI protection model. With the development of two industrial CHERI-enabled processors over the past two years, Arm’s Morello and Microsoft’s CHERIoT, CHERI may offer the fastest path to widely deployed memory safety.
Description
Journal Title
IEEE Security and Privacy
Conference Name
Journal ISSN
1540-7993
1558-4046
1558-4046
Volume Title
Publisher
Institute of Electrical and Electronics Engineers
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Except where otherwised noted, this item's license is described as Attribution 4.0 International
Sponsorship
Innovate UK (105694)
Engineering and Physical Sciences Research Council (EP/K008528/1)
European Research Council (789108)
EPSRC (EP/V000292/1)
Engineering and Physical Sciences Research Council (EP/K008528/1)
European Research Council (789108)
EPSRC (EP/V000292/1)
Additional support was received from Arm, Google, and Microsoft.