Reliability challenges of gate dielectric materials in transistors

Abstract

Abstract The gate dielectric plays a critical role in field‐effect transistors since it determines the capability of gate control and the reliability of the device. In modern large scale integrated circuits, the stacking of high‐k oxides has become an indispensable strategy to enable the continuous shrinking of the device. However, the multiple interfaces, various kinds and large number of defects have brought about significant reliability issues such as threshold voltage shift, gate leakage current, random noise, hysteresis, fixed charges and so on. Effectively dealing with these reliability issues has become the main challenge of dielectric design. On the other hand, with the emerging of two‐dimensional (2D) channel materials, traditional oxide dielectrics turn out to be nonideal due to their surface dangling bonds. The development and design of new gate dielectrics become urgent and attractive. In this review, we will summarize the advantages and challenges of different dielectrics that are applicable to several mainstream channel materials, including Si, SiC, GaN and 2D materials. For each kind of dielectric, possible strategies to improve its reliability are discussed.