A case for efficient accelerator design space exploration via Bayesian optimization
Accepted version
Peer-reviewed
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Abstract
In this paper we propose using machine learning to improve the design of deep neural network hardware accelerators. We show how to adapt multi-objective Bayesian optimization to overcome a challenging design problem: Optimizing deep neural network hardware accelerators for both accuracy and energy efficiency. DNN accelerators exhibit all aspects of a challenging optimization space: The landscape is rough, evaluating designs is expensive, the objectives compete with each other, and both design spaces (algorithmic and microarchitectural) are unwieldy. With multi-objective Bayesian optimization, the design space exploration is made tractable and the design points found vastly outperform traditional methods across all metrics of interest.
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Keywords
accelerator design space exploration, bayesian optimization, machine learning, deep neural network hardware accelerators, DNN accelerators, optimization space
Journal Title
Proceedings of the International Symposium on Low Power Electronics and Design
Conference Name
ACM/IEEE International Symposium on Low Power Electronics and Design
Journal ISSN
1533-4678
Volume Title
Publisher
IEEE