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Rapid codesign of a soft vector processor and its compiler


Type

Conference Object

Change log

Authors

Naylor, M 
Moore, SW 

Abstract

Despite a decade of activity in the development of soft vector processors for FPGAs, high-level language support remains thin. We attribute this problem to a design method in which the high-level vector programming interface is only really considered once the processor architecture has been perfected, by which point the designer may be committed to the timeconsuming development of a complicated compiler. In this paper, we present the codesign of a soft vector processor and a lightweight compiler, which together lift the level of abstraction for the programmer while allowing a rapid compiler implementation phase.We demonstrate the effectiveness of our approach on a range of applications from digital signal processing, neuroscience, and machine learning.

Description

Keywords

33 Built Environment and Design, 40 Engineering, 4008 Electrical Engineering, 4009 Electronics, Sensors and Digital Hardware, 3301 Architecture

Journal Title

Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014

Conference Name

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

Journal ISSN

Volume Title

Publisher

IEEE
Sponsorship
Engineering and Physical Sciences Research Council (EP/G015783/1)
This work is sponsored by EPSRC grant EP/G015783/1.