Encapsulation of graphene transistors and vertical device integration by interface engineering with atomic layer deposited oxide
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Peer-reviewed
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Change log
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Abstract
We demonstrate a simple, scalable approach to achieve encapsulated graphene transistors with negligible gate hysteresis, low doping levels and enhanced mobility compared to as-fabricated devices. We engineer the interface between graphene and atomic layer deposited (ALD) Al
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Journal ISSN
2053-1583
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Sponsorship
European Research Council (279342)
Engineering and Physical Sciences Research Council (EP/L020963/1)
Engineering and Physical Sciences Research Council (EP/L016087/1)
Engineering and Physical Sciences Research Council (EP/M506485/1)