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dc.contributor.authorAlexander-Webber, Jack Allenen
dc.contributor.authorSagade, Abhayen
dc.contributor.authorAria, AIen
dc.contributor.authorVan Veldhoven, ZAen
dc.contributor.authorBraeuninger-Weimer, Philippen
dc.contributor.authorWang, Ruizhien
dc.contributor.authorCabrero-Vilatela, Aen
dc.contributor.authorMartin, M-Ben
dc.contributor.authorSui, Jen
dc.contributor.authorConnolly, MRen
dc.contributor.authorHofmann, Stephanen
dc.date.accessioned2017-02-09T11:55:25Z
dc.date.available2017-02-09T11:55:25Z
dc.date.issued2017-03-01en
dc.identifier.issn2053-1583
dc.identifier.urihttps://www.repository.cam.ac.uk/handle/1810/262403
dc.description.abstractWe demonstrate a simple, scalable approach to achieve encapsulated graphene transistors with negligible gate hysteresis, low doping levels and enhanced mobility compared to as-fabricated devices. We engineer the interface between graphene and atomic layer deposited (ALD) Al$_{2}$O$_{3}$ by tailoring the growth parameters to achieve effective device encapsulation whilst enabling the passivation of charge traps in the underlying gate dielectric. We relate the passivation of charge trap states in the vicinity of the graphene to conformal growth of ALD oxide governed by $\textit{in situ}$ gaseous H$_{2}$O pretreatments. We demonstrate the long term stability of such encapsulation techniques and the resulting insensitivity towards additional lithography steps to enable vertical device integration of graphene for multi-stacked electronics fabrication.
dc.description.sponsorshipThis work was supported by the EPSRC (Grant Nos. EP/K016636/1, GRAPHTED and EP/L020963/1) and the ERC (Grant No. 279342, InsituNANO). JAA-W acknowledges a Research Fellowship from Churchill College, Cambridge. JS acknowledges support from NUDT. ZAVV acknowledges funding from ESPRC grant EP/L016087/1. ACV acknowledges the Conacyt Cambridge Scholarship and the Roberto Rocca Fellowship. RW acknowledges EPSRC Doctoral Training Award (EP/M506485/1).
dc.languageengen
dc.language.isoenen
dc.publisherInstitute of Physics
dc.rightsAttribution 4.0 Internationalen
dc.rightsAttribution 4.0 Internationalen
dc.rightsAttribution 4.0 Internationalen
dc.rightsAttribution 4.0 Internationalen
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.subjectgrapheneen
dc.subjectatomic layer depositionen
dc.subjectdevice integrationen
dc.subjecthysteresisen
dc.subjectair stabilityen
dc.subjectAl$_{2}$O$_{3}$en
dc.titleEncapsulation of graphene transistors and vertical device integration by interface engineering with atomic layer deposited oxideen
dc.typeArticle
prism.issueIdentifier1en
prism.number011008en
prism.publicationDate2017en
prism.publicationName2D Materialsen
prism.volume4en
dc.identifier.doi10.17863/CAM.7669
dcterms.dateAccepted2016-11-07en
rioxxterms.versionofrecord10.1088/2053-1583/4/1/011008en
rioxxterms.versionVoRen
rioxxterms.licenseref.urihttp://creativecommons.org/licenses/by/4.0/en
rioxxterms.licenseref.startdate2017-03-01en
dc.contributor.orcidAlexander-Webber, Jack Allen [0000-0002-9374-7423]
dc.contributor.orcidSagade, Abhay [0000-0002-3299-7103]
dc.contributor.orcidBraeuninger-Weimer, Philipp [0000-0001-8677-1647]
dc.contributor.orcidWang, Ruizhi [0000-0002-3914-8649]
dc.contributor.orcidHofmann, Stephan [0000-0001-6375-1459]
dc.identifier.eissn2053-1583
rioxxterms.typeJournal Article/Reviewen
pubs.funder-project-idEPSRC (EP/K016636/1)
pubs.funder-project-idEuropean Research Council (279342)
pubs.funder-project-idEPSRC (EP/L020963/1)
pubs.funder-project-idEPSRC (EP/L016087/1)
pubs.funder-project-idEPSRC (EP/M506485/1)
cam.issuedOnline2016-12-01en
cam.orpheus.successThu Jan 30 12:57:05 GMT 2020 - The item has an open VoR version.*
rioxxterms.freetoread.startdate2100-01-01


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Attribution 4.0 International
Except where otherwise noted, this item's licence is described as Attribution 4.0 International